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powerpc, 8xx: Add support for MCR3000 board from CSSI

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CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000
and CMPC885 which are respectively based on MPC866 and MPC885 processors.

This patch adds support for the first board.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
This commit is contained in:
Christophe Leroy 2017-07-07 10:16:42 +02:00 committed by Tom Rini
parent dd7ff4721a
commit 53193a4f07
11 changed files with 604 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.travis.yml
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@ -205,6 +205,8 @@ matrix:
- BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
- env:
- BUILDMAN="mpc86xx"
- env:
- BUILDMAN="mpc8xx"
- env:
- BUILDMAN="siemens"
- env:

5
arch/powerpc/cpu/mpc8xx/Kconfig
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@ -8,6 +8,9 @@ choice
prompt "Target select"
optional
config TARGET_MCR3000
bool "Support MCR3000 board from CSSI"
endchoice
choice
@ -167,4 +170,6 @@ config SYS_OR7_PRELIM
config SYS_IMMR
hex "Value for IMMR"
source "board/cssi/MCR3000/Kconfig"
endmenu

6
board/cssi/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
BOARDS from CS Systemes d'Information
M: Christophe Leroy <christophe.leroy@c-s.fr>
S: Maintained
F: board/cssi/
F: include/configs/MCR3000.h
F: configs/MCR3000_defconfig

15
board/cssi/MCR3000/Kconfig Normal file
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@ -0,0 +1,15 @@
if TARGET_MCR3000
config SYS_BOARD
default "MCR3000"
config SYS_VENDOR
default "cssi"
config SYS_CONFIG_NAME
default "MCR3000"
config SYS_TEXT_BASE
default 0x04000000
endif

144
board/cssi/MCR3000/MCR3000.c Normal file
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@ -0,0 +1,144 @@
/*
* Copyright (C) 2010-2017 CS Systemes d'Information
* Florent Trinh Thai <florent.trinh-thai@c-s.fr>
* Christophe Leroy <christophe.leroy@c-s.fr>
*
* Board specific routines for the MCR3000 board
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <hwconfig.h>
#include <mpc8xx.h>
#include <fdt_support.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static const uint cs1_dram_table_66[] = {
/* DRAM - single read. (offset 0 in upm RAM) */
0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/* DRAM - burst read. (offset 8 in upm RAM) */
0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/* DRAM - single write. (offset 18 in upm RAM) */
0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
/* DRAM - burst write. (offset 20 in upm RAM) */
0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/* refresh (offset 30 in upm RAM) */
0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
/* init */
0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
/* exception. (offset 3c in upm RAM) */
0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
};
int ft_board_setup(void *blob, bd_t *bd)
{
const char *sync = "receive";
ft_cpu_setup(blob, bd);
/* BRG */
do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
bd->bi_busfreq, 1);
/* MAC addr */
fdt_fixup_ethernet(blob);
/* Bus Frequency for CPM */
do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
/* E1 interface - Set data rate */
do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
/* E1 interface - Set channel phase to 0 */
do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
/* E1 interface - rising edge sync pulse transmit */
do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
sync, strlen(sync), 1);
return 0;
}
int checkboard(void)
{
serial_puts("BOARD: MCR3000 CSSI\n");
return 0;
}
int dram_init(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
printf("UPMA init for SDRAM (CAS latency 2), ");
printf("init address 0x%08x, size ", (int)dram_init);
/* Configure UPMA for cs1 */
upmconfig(UPMA, (uint *)cs1_dram_table_66,
sizeof(cs1_dram_table_66) / sizeof(uint));
udelay(10);
out_be16(&memctl->memc_mptpr, 0x0200);
out_be32(&memctl->memc_mamr, 0x14904000);
udelay(10);
out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
udelay(10);
out_be32(&memctl->memc_mcr, 0x80002830);
out_be32(&memctl->memc_mar, 0x00000088);
out_be32(&memctl->memc_mcr, 0x80002038);
udelay(200);
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
SDRAM_MAX_SIZE);
return 0;
}
int misc_init_r(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
iop8xx_t __iomem *iop = &immr->im_ioport;
/* Set port C13 as GPIO (BTN_ACQ_AL) */
clrbits_be16(&iop->iop_pcpar, 0x4);
clrbits_be16(&iop->iop_pcdir, 0x4);
/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
setenv("bootdelay", "60");
return 0;
}
int board_early_init_f(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/*
* Erase FPGA(s) for reboot
*/
clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
udelay(1); /* Wait more than 300ns */
setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
return 0;
}

10
board/cssi/MCR3000/Makefile Normal file
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@ -0,0 +1,10 @@
#
# Copyright (C) 2010-2017 CS Systemes d'Information
# Christophe Leroy <christophe.leroy@c-s.fr>
#
# SPDX-License-Identifier: GPL-2.0+
#
#
obj-y += MCR3000.o
obj-$(CONFIG_CMD_NAND) += nand.o

65
board/cssi/MCR3000/nand.c Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (C) 2010-2017 CS Systemes d'Information
* Florent Trinh Thai <florent.trinh-thai@c-s.fr>
* Christophe Leroy <christophe.leroy@c-s.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#define BIT_CLE ((unsigned short)0x0800)
#define BIT_ALE ((unsigned short)0x0400)
#define BIT_NCE ((unsigned short)0x1000)
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
unsigned short pddat = 0;
/* The hardware control change */
if (ctrl & NAND_CTRL_CHANGE) {
pddat = in_be16(&immr->im_ioport.iop_pddat);
/* Clearing ALE and CLE */
pddat &= ~(BIT_CLE | BIT_ALE);
/* Driving NCE pin */
if (ctrl & NAND_NCE)
pddat &= ~BIT_NCE;
else
pddat |= BIT_NCE;
/* Driving CLE and ALE pin */
if (ctrl & NAND_CLE)
pddat |= BIT_CLE;
if (ctrl & NAND_ALE)
pddat |= BIT_ALE;
out_be16(&immr->im_ioport.iop_pddat, pddat);
}
/* Writing the command */
if (cmd != NAND_CMD_NONE)
out_8(this->IO_ADDR_W, cmd);
}
int board_nand_init(struct nand_chip *nand)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/* Set GPIO Port */
setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_hwcontrol;
return 0;
}

91
board/cssi/MCR3000/u-boot.lds Normal file
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@ -0,0 +1,91 @@
/*
* Copyright (C) 2010-2017 CS Systemes d'Information
* Christophe Leroy <christophe.leroy@c-s.fr>
*
* (C) Copyright 2001-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Modified by Yuli Barcohen <yuli@arabellasw.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text)
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
arch/powerpc/lib/built-in.o (.text*)
board/cssi/MCR3000/built-in.o (.text*)
disk/built-in.o (.text*)
drivers/net/built-in.o (.text*)
*(.text)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

88
configs/MCR3000_defconfig Normal file
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@ -0,0 +1,88 @@
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_MCR3000=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_NET=y
CONFIG_CMD_DHCP=y
# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_SYS_PROMPT="S3K> "
CONFIG_NETDEVICES=y
CONFIG_MPC8XX_FEC=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_MD5SUM is not set
# CONFIG_CMD_MISC is not set
# CONFIG_CMD_SETGETDCR is not set
# CONFIG_CMD_SHA1 is not set
# CONFIG_CMD_SOURCE is not set
CONFIG_CMD_IMMAP=y
CONFIG_SYS_IMMR=0xFF000000
CONFIG_SYS_OR0_PRELIM=0xFFC00926
CONFIG_SYS_BR0_PRELIM=0x04000801
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0x00000081
CONFIG_SYS_OR1_PRELIM=0xFE000E00
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0x08000801
CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0x0C000401
CONFIG_SYS_OR3_PRELIM=0xFFFF8142
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0x10000801
CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
CONFIG_SYS_BR5_PRELIM_BOOL=y
CONFIG_SYS_BR5_PRELIM=0x14000801
CONFIG_SYS_OR5_PRELIM=0xFFFF8916
CONFIG_SYS_BR6_PRELIM_BOOL=y
CONFIG_SYS_BR6_PRELIM=0x18000801
CONFIG_SYS_OR6_PRELIM=0xFFFF0908
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x1C000001
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_SYS_SYPCR=0xFFFFFF8F
CONFIG_SYS_SIUMCR=0x00600400
CONFIG_SYS_TBSCR=0x00C3
CONFIG_SYS_PISCR=0x0000
CONFIG_SYS_PLPRCR_BOOL=y
CONFIG_SYS_PLPRCR=0x00460004
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_DER=0x2002000F
CONFIG_AUTOBOOT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
CONFIG_AUTOBOOT_DELAY_STR="root"
CONFIG_OF_BOARD_SETUP=y
CONFIG_LZMA=y
CONFIG_SHA256=y

20
drivers/net/mpc8xx_fec.c
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@ -413,6 +413,26 @@ static void fec_pin_init(int fecidx)
*/
out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
#if defined(CONFIG_TARGET_MCR3000)
out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
out_be16(&immr->im_ioport.iop_padir, 0x04F0);
out_be16(&immr->im_ioport.iop_paodr, 0x0000);
out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
out_be16(&immr->im_ioport.iop_pcint, 0x0000);
out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
setbits_be32(&immr->im_ioport.utmode, 0x80);
#endif
#endif
#endif /* CONFIG_ETHER_ON_FEC1 */

158
include/configs/MCR3000.h Normal file
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@ -0,0 +1,158 @@
/*
* Copyright (C) 2010-2017 CS Systemes d'Information
* Christophe Leroy <christophe.leroy@c-s.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_EXTRA_ENV_SETTINGS \
"sdram_type=SDRAM\0" \
"flash_type=AM29LV160DB\0" \
"loadaddr=0x400000\0" \
"filename=uImage.lzma\0" \
"nfsroot=/opt/ofs\0" \
"dhcp_ip=ip=:::::eth0:dhcp\0" \
"console_args=console=ttyCPM0,115200N8\0" \
"flashboot=setenv bootargs " \
"${console_args} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"mcr3k:eth0:off;" \
"${ofl_args}; " \
"bootm 0x04060000 - 0x04050000\0" \
"tftpboot=setenv bootargs " \
"${console_args} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"mcr3k:eth0:off " \
"${ofl_args}; " \
"tftp ${loadaddr} ${filename};" \
"tftp 0xf00000 mcr3000.dtb;" \
"bootm ${loadaddr} - 0xf00000\0" \
"netboot=dhcp ${loadaddr} ${filename};" \
"tftp 0xf00000 mcr3000.dtb;" \
"setenv bootargs " \
"root=/dev/nfs rw " \
"${console_args} " \
"${dhcp_ip};" \
"bootm ${loadaddr} - 0xf00000\0" \
"nfsboot=setenv bootargs " \
"root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
"${console_args} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"mcr3k:eth0:off;" \
"bootm 0x04060000 - 0x04050000\0" \
"dhcpboot=dhcp ${loadaddr} ${filename};" \
"tftp 0xf00000 mcr3000.dtb;" \
"setenv bootargs " \
"${console_args} " \
"${dhcp_ip} " \
"${ofl_args}; " \
"bootm ${loadaddr} - 0xf00000\0"
#define CONFIG_BOOTDELAY 5
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_NETMASK 255.0.0.0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_BOOTARGS "ubi.mtd=4 root=ubi0:rootfs rw " \
"rootfstype=ubifs rootflags=sync " \
"console=ttyCPM0,115200N8 " \
"ip=${ipaddr}:::${netmask}:mcr3k:eth0:off"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_WATCHDOG 1 /* watchdog enabled */
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_CMDLINE_EDITING 1
#ifdef CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "S3K> "
#endif
#define CONFIG_SYS_MEMTEST_START 0x00002000
#define CONFIG_SYS_MEMTEST_END 0x00800000
#define CONFIG_SYS_LOAD_ADDR 0x200000
#define CONFIG_SYS_HZ 1000
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00
#define CONFIG_SYS_GBL_DATA_SIZE 64
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 35
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
/* Environment Configuration */
/* environment is in FLASH */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_OVERWRITE 1
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
/* Ethernet configuration part */
#define CONFIG_SYS_DISCOVER_PHY 1
#ifdef CONFIG_MPC8XX_FEC
#define CONFIG_MII_INIT 1
#endif
/* NAND configuration part */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x0C000000
/* Internal Definitions */
/* Boot Flags*/
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
/* Misc Settings */
#define CONFIG_CMD_REGINFO
#endif /* __CONFIG_H */