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am335x:Handle worst case scenario for Errata 1.0.24

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In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.

Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Adapt to current framework]
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Steve Kipisz
2013-08-14 10:51:31 -04:00
committed by Tom Rini
parent 9721027aae
commit 52f7d8442e
6 changed files with 30 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv7/am33xx/board.c
View File

@@ -144,6 +144,8 @@ int arch_misc_init(void)
*/
__weak void am33xx_spl_board_init(void)
{
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
static void rtc32k_enable(void)

8
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
View File

@@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
.cm_div_m2_dpll = CM_WKUP + 0xA0,
};
const struct dpll_params dpll_mpu = {
struct dpll_params dpll_mpu_opp100 = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
const struct dpll_params dpll_core_opp100 = {
1000, OSC-1, -1, -1, 10, 8, 4};
const struct dpll_params dpll_mpu = {
MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
50, OSC-1, -1, -1, 1, 1, 1};
const struct dpll_params dpll_per = {
960, OSC-1, 5, -1, -1, -1, -1};

2
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
View File

@@ -29,5 +29,7 @@
#define UART_SMART_IDLE_EN (0x1 << 0x3)
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;
#endif /* endif _CLOCKS_AM33XX_H_ */