board: gateworks: venice: determine dram size at runtime
The SPL does not update the memory node with the dram size from EEPROM but instead we can use get_ram_size which does a simple memory test to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that is the max used on the Venice boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
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@ -21,19 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_phys_sdram_size(phys_size_t *size)
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{
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const fdt64_t *val;
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int offset;
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int len;
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/* get size from dt which SPL updated per EEPROM config */
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offset = fdt_path_offset(gd->fdt_blob, "/memory");
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if (offset < 0)
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if (!size)
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return -EINVAL;
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val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
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if (len < sizeof(*val) * 2)
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return -EINVAL;
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*size = get_unaligned_be64(&val[1]);
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*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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@ -83,7 +83,7 @@
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/* SDRAM configuration */
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
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#define PHYS_SDRAM_SIZE SZ_4G
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#define CONFIG_SYS_BOOTM_LEN SZ_256M
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/* UART */
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@ -80,7 +80,7 @@
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/* SDRAM configuration */
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_1G
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#define PHYS_SDRAM_SIZE SZ_4G
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#define CONFIG_SYS_BOOTM_LEN SZ_256M
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/* UART */
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