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dm: sound: exynos: Correct codec bus addresses

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For snow the codec is at address 0x11 on the i2c bus, in 7-bit format.
The device tree and code are in 8-bit format (i.e. shifted left one bit).
Fix both. Fix pit in a similar way.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2018-12-10 10:37:30 -07:00
parent a1efd49ee2
commit 51b06dc40b
4 changed files with 11 additions and 12 deletions
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4
arch/arm/dts/exynos5250-snow.dts
View File

@ -214,8 +214,8 @@
}; };
}; };
soundcodec@22 { soundcodec@11 {
reg = <0x22>; reg = <0x11>;
compatible = "maxim,max98095-codec"; compatible = "maxim,max98095-codec";
}; };
}; };

8
arch/arm/dts/exynos5420-peach-pit.dts
View File

@ -69,10 +69,10 @@
i2c@12CD0000 { /* i2c7 */ i2c@12CD0000 { /* i2c7 */
clock-frequency = <100000>; clock-frequency = <100000>;
soundcodec@20 { soundcodec@10 {
reg = <0x20>; reg = <0x10>;
compatible = "maxim,max98090-codec"; compatible = "maxim,max98090-codec";
}; };
edp-lvds-bridge@48 { edp-lvds-bridge@48 {
compatible = "parade,ps8625"; compatible = "parade,ps8625";

8
arch/arm/dts/exynos5800-peach-pi.dts
View File

@ -81,10 +81,10 @@
i2c@12CD0000 { /* i2c7 */ i2c@12CD0000 { /* i2c7 */
clock-frequency = <100000>; clock-frequency = <100000>;
soundcodec@20 { soundcodec@10 {
reg = <0x20>; reg = <0x10>;
compatible = "maxim,max98090-codec"; compatible = "maxim,max98090-codec";
}; };
}; };
sound@3830000 { sound@3830000 {

3
drivers/sound/max98095.c
View File

@ -569,8 +569,7 @@ int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
i2c_set_bus_num(pcodec_info.i2c_bus); i2c_set_bus_num(pcodec_info.i2c_bus);
/* shift the device address by 1 for 7 bit addressing */ max98095_info.i2c_addr = pcodec_info.i2c_dev_addr;
max98095_info.i2c_addr = pcodec_info.i2c_dev_addr >> 1;
ret = max98095_device_init(&max98095_info); ret = max98095_device_init(&max98095_info);
if (ret < 0) { if (ret < 0) {
debug("%s: max98095 codec chip init failed\n", __func__); debug("%s: max98095 codec chip init failed\n", __func__);