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Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-10-04 11:27:55 -04:00
commit 50c84208ad
2866 changed files with 22972 additions and 26385 deletions
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25
.azure-pipelines.yml
View File

@ -2,7 +2,7 @@ variables:
windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@ -195,6 +195,9 @@ jobs:
evb_ast2500:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"
@ -254,6 +257,12 @@ jobs:
r2dplus_tulip:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
sifive_unleashed_sdcard:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id sdcard_qemu"
sifive_unleashed_spi-nor:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"
xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu"
@ -289,7 +298,7 @@ jobs:
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
@ -302,6 +311,18 @@ jobs:
cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
# create sdcard / spi-nor images for sifive unleashed using genimage
if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
mkdir -p root;
cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
fi
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt

34
.gitlab-ci.yml
View File

@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
# We run some tests in different order, to catch some failures quicker.
stages:
@ -23,7 +23,7 @@ stages:
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
@ -40,6 +40,18 @@ stages:
- cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
- cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
- cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
# create sdcard / spi-nor images for sifive unleashed using genimage
- if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
mkdir -p root;
cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt
@ -204,6 +216,12 @@ sandbox_flattree test.py:
TEST_PY_BD: "sandbox_flattree"
<<: *buildman_and_testpy_dfn
vexpress_ca9x4 test.py:
variables:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
integratorcp_cm926ejs test.py:
variables:
TEST_PY_BD: "integratorcp_cm926ejs"
@ -317,6 +335,18 @@ r2dplus_tulip test.py:
TEST_PY_ID: "--id tulip_qemu"
<<: *buildman_and_testpy_dfn
sifive_unleashed_sdcard test.py:
variables:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id sdcard_qemu"
<<: *buildman_and_testpy_dfn
sifive_unleashed_spi-nor test.py:
variables:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"
<<: *buildman_and_testpy_dfn
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"

1
.mailmap
View File

@ -29,6 +29,7 @@ Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Markus Klotzbuecher <mk@denx.de>

27
Kconfig
View File

@ -83,7 +83,6 @@ config CC_OPTIMIZE_FOR_SIZE
config OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
@ -93,7 +92,6 @@ config OPTIMIZE_INLINING
config SPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in SPL"
depends on SPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
@ -106,7 +104,6 @@ config ARCH_SUPPORTS_LTO
config LTO
bool "Enable Link Time Optimizations"
depends on ARCH_SUPPORTS_LTO
default n
help
This option enables Link Time Optimization (LTO), a mechanism which
allows the compiler to optimize between different compilation units.
@ -127,7 +124,6 @@ config LTO
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
@ -249,8 +245,11 @@ config SYS_MALLOC_F_LEN
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
default 0x2000000 if ARCH_ROCKCHIP
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S
default 0x200000 if ARCH_BMIPS || X86
default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S
default 0x400000
help
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
@ -307,7 +306,6 @@ if EXPERT
config SYS_MALLOC_DEFAULT_TO_INIT
bool "Default malloc to init while reserving the memory for it"
default n
help
It may happen that one needs to move the dynamic allocation
from one to another memory range, eg. when moving the malloc
@ -389,6 +387,20 @@ config SYS_LDSCRIPT
Path within the source tree to the linker script to use for the
main U-Boot binary.
config SYS_LOAD_ADDR
hex "Address in memory to use by default"
default 0x01000000 if ARCH_SOCFPGA
default 0x02000000 if PPC || X86
default 0x22000000 if MACH_SUN9I
default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
default 0x80800000 if ARCH_MX7
default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
help
Address in memory to use as the default safe load address.
config ERR_PTR_OFFSET
hex
default 0x0
@ -423,7 +435,6 @@ config SYS_HAS_SRAM
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
default y if TARGET_TRICORDER
default n
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.

2
Licenses/lgpl-2.0.txt
View File

@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based
on the Library (independent of the use of the Library in a tool for
writing it). Whether that is true depends on what the Library does
and what the program that uses the Library does.
1. You may copy and distribute verbatim copies of the Library's
complete source code as you receive it, in any medium, provided that
you conspicuously and appropriately publish on each copy an

16
MAINTAINERS
View File

@ -312,6 +312,7 @@ F: arch/arm/mach-at91/
F: board/atmel/
F: drivers/cpu/at91_cpu.c
F: drivers/misc/microchip_flexcom.c
F: include/dt-bindings/mfd/atmel-flexcom.h
F: drivers/timer/mchp-pit64b-timer.c
ARM NEXELL S5P4418
@ -525,7 +526,12 @@ R: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: arch/arm/dts/ste-*
F: arch/arm/mach-u8500/
F: drivers/gpio/nmk_gpio.c
F: drivers/phy/phy-ab8500-usb.c
F: drivers/power/pmic/ab8500.c
F: drivers/timer/nomadik-mtu-timer.c
F: drivers/usb/musb-new/ux500.c
F: drivers/video/mcde_simple.c
ARM UNIPHIER
S: Orphan (Since 2020-09)
@ -769,6 +775,16 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
F: drivers/i2c/
KWBIMAGE / KWBOOT TOOLS
M: Pali Rohár <pali@kernel.org>
M: Marek Behún <marek.behun@nic.cz>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: doc/README.kwbimage
F: doc/kwboot.1
F: tools/kwb*
LOGGING
M: Simon Glass <sjg@chromium.org>
S: Maintained

27
Makefile
View File

@ -327,14 +327,14 @@ os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \
$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
# Snow Leopards build environment has no longer restrictions as described above
HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc")
KBUILD_HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp")
KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
# macOS Mojave (10.14.X)
# macOS Mojave (10.14.X)
# Undefined symbols for architecture x86_64: "_PyArg_ParseTuple"
KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "")
endif
@ -813,23 +813,9 @@ libs-y += fs/
libs-y += net/
libs-y += disk/
libs-y += drivers/
libs-y += drivers/dma/
libs-y += drivers/gpio/
libs-y += drivers/net/
libs-y += drivers/net/phy/
libs-y += drivers/power/ \
drivers/power/domain/ \
drivers/power/fuel_gauge/ \
drivers/power/mfd/ \
drivers/power/pmic/ \
drivers/power/battery/ \
drivers/power/regulator/
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/cdns3/
libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
@ -1306,10 +1292,6 @@ u-boot.ldr: u-boot
# Use 'make BINMAN_VERBOSE=3' to set vebosity level
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
# Tell binman whether we have a devicetree for SPL and TPL
have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL))
have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL))
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \
@ -1323,7 +1305,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
-a scp-path=$(SCP) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
-a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \
-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
-a tpl-dtb=$(CONFIG_SPL_OF_REAL) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@ -1756,7 +1739,7 @@ endif
# May be overridden by arch/$(ARCH)/config.mk
ifdef CONFIG_LTO
quiet_cmd_u-boot__ ?= LTO $@
cmd_u-boot__ ?= \
cmd_u-boot__ ?= \
$(CC) -nostdlib -nostartfiles \
$(LTO_FINAL_LDFLAGS) $(c_flags) \
$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \

180
README
View File

@ -300,7 +300,6 @@ board_init_r():
- loads U-Boot or (in falcon mode) Linux
Configuration Options:
----------------------
@ -465,10 +464,6 @@ The following options need to be configured:
Board config to use DDR3L. It can be enabled for SoCs with
DDR3L controllers.
CONFIG_SYS_FSL_DDR4
Board config to use DDR4. It can be enabled for SoCs with
DDR4 controllers.
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
@ -481,15 +476,6 @@ The following options need to be configured:
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details
CONFIG_SYS_FSL_PBL_RCW
It adds PBI(pre-boot instructions) commands in u-boot build image.
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
CONFIG_SYS_FSL_DDR_BE
Defines the DDR controller register space as Big Endian
@ -599,16 +585,6 @@ The following options need to be configured:
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
CONFIG_MACH_TYPE [relevant for ARM only][mandatory]
This setting is mandatory for all boards that have only one
machine type and must be used to specify the machine type
number as it appears in the ARM machine registry
(see https://www.arm.linux.org.uk/developer/machines/).
Only boards that have multiple machine types supported
in a single configuration file and the machine type is
runtime discoverable, do not have to use this setting.
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
@ -671,11 +647,6 @@ The following options need to be configured:
time on others. This setting #define's the initial
value of the "loads_echo" environment variable.
- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
CONFIG_KGDB_BAUDRATE
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
- Removal of commands
If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line
@ -879,17 +850,6 @@ The following options need to be configured:
Support for National dp8382[01] gigabit chips.
- NETWORK Support (other):
CONFIG_DRIVER_AT91EMAC
Support for AT91RM9200 EMAC.
CONFIG_RMII
Define this to use reduced MII inteface
CONFIG_DRIVER_AT91EMAC_QUIET
If this defined, the driver is quiet.
The driver doen't show link status messages.
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
@ -1461,129 +1421,7 @@ The following options need to be configured:
In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
- I2C Support: CONFIG_SYS_I2C_LEGACY
Note: This is deprecated in favour of driver model. Use
CONFIG_DM_I2C instead.
This enable the legacy i2c subsystem, and will allow you to use
i2c commands at the u-boot command line (as long as you set
CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
for defining speed and slave address
- activate second bus with I2C_SOFT_DECLARATIONS2 define
CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
for defining speed and slave address
- activate third bus with I2C_SOFT_DECLARATIONS3 define
CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
for defining speed and slave address
- activate fourth bus with I2C_SOFT_DECLARATIONS4 define
CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
for defining speed and slave address
- drivers/i2c/fsl_i2c.c:
- activate i2c driver with CONFIG_SYS_I2C_FSL
define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
bus.
- If your board supports a second fsl i2c bus, define
CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
CONFIG_SYS_FSL_I2C2_SPEED for the speed and
CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
second bus.
- drivers/i2c/tegra_i2c.c:
- activate this driver with CONFIG_SYS_I2C_TEGRA
- This driver adds 4 i2c buses with a fix speed from
100000 and the slave addr 0!
- drivers/i2c/ppc4xx_i2c.c
- activate this driver with CONFIG_SYS_I2C_PPC4XX
- CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
- CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
- drivers/i2c/i2c_mxc.c
- activate this driver with CONFIG_SYS_I2C_MXC
- enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
- enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
- enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
- enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
- define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
- define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
- define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
- define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
If those defines are not set, default value is 100000
for speed, and 0 for slave.
- drivers/i2c/rcar_i2c.c:
- activate this driver with CONFIG_SYS_I2C_RCAR
- This driver adds 4 i2c buses
- drivers/i2c/sh_i2c.c:
- activate this driver with CONFIG_SYS_I2C_SH
- This driver adds from 2 to 5 i2c buses
- CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
- CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
- CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
- CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
- CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
- CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
- CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
- CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
- CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
- CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
- CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
- drivers/i2c/omap24xx_i2c.c
- activate this driver with CONFIG_SYS_I2C_OMAP24XX
- CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
- CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
- CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
- CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
- CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
- CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
- CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
- CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
- CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
- CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
- drivers/i2c/s3c24x0_i2c.c:
- activate this driver with CONFIG_SYS_I2C_S3C24X0
- This driver adds i2c buses (11 for Exynos5250, Exynos5420
9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
with a fix speed from 100000 and the slave addr 0!
- drivers/i2c/ihs_i2c.c
- activate this driver with CONFIG_SYS_I2C_IHS
- CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
- CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
- CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
- CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
- CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
- CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
- CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
- CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
- CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
- CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
- CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
- CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
- activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
- CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
- CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
- CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
- CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
- CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
- CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
- CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
- CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
additional defines:
- I2C Support:
CONFIG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
@ -2873,22 +2711,6 @@ Low Level (hardware related) configuration options:
This only takes effect if the memory commands are activated
globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT
[ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
Normally this variable MUST NOT be defined. The only
exception is when U-Boot is loaded (to RAM) by some
other boot loader or by a debugger which performs
these initializations itself.
- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
[ARM926EJ-S only] This allows just the call to lowlevel_init()
to be skipped. The normal CP15 init (such as enabling the
instruction cache) is still performed.
- CONFIG_SPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the SPL (as opposed to the TPL or U-Boot

1
api/Kconfig
View File

@ -2,7 +2,6 @@ menu "API"
config API
bool "Enable U-Boot API"
default n
help
This option enables the U-Boot API. See api/README for more information.

90
arch/Kconfig
View File

@ -7,6 +7,27 @@ config HAVE_ARCH_IOREMAP
config NEEDS_MANUAL_RELOC
bool
config SYS_CACHE_SHIFT_4
bool
config SYS_CACHE_SHIFT_5
bool
config SYS_CACHE_SHIFT_6
bool
config SYS_CACHE_SHIFT_7
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
default 16 if SYS_CACHE_SHIFT_4
# Fall-back for MIPS
default 32 if MIPS
config LINKER_LIST_ALIGN
int
default 32 if SANDBOX
@ -29,6 +50,7 @@ config ARC
select DM
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_7
select TIMER
config ARM
@ -44,6 +66,7 @@ config M68K
select NEEDS_MANUAL_RELOC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
select SYS_CACHE_SHIFT_4
select SUPPORT_OF_CONTROL
config MICROBLAZE
@ -97,7 +120,7 @@ config RISCV
imply SPL_OF_CONTROL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_SERIAL
imply SPL_TIMER
config SANDBOX
@ -122,6 +145,7 @@ config SANDBOX
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN
imply BITREVERSE
@ -187,6 +211,7 @@ config X86
select OF_CONTROL
select PCI
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_6
select TIMER
select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
@ -233,9 +258,9 @@ config X86
imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_SERIAL
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
imply SPL_SPI
imply SPL_OF_CONTROL
imply SPL_TIMER
imply SPL_REGMAP
@ -247,7 +272,7 @@ config X86
imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SERIAL_SUPPORT
imply TPL_SERIAL
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
@ -325,6 +350,63 @@ config SYS_DISABLE_DCACHE_OPS
Note that, its up to the individual architectures to implement
this functionality.
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on ARM || NDS32 || MIPS || RISCV
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config SPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on SPL && (ARM || NDS32 || MIPS || RISCV)
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config TPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on SPL && ARM
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY"
depends on ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
config SPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY"
depends on SPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
config TPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY"
depends on TPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"

5
arch/arc/Kconfig
View File

@ -104,13 +104,11 @@ endchoice
config CPU_BIG_ENDIAN
bool "Enable Big Endian Mode"
default n
help
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
bool "Do not enable icache"
default n
help
Do not enable instruction cache in U-Boot.
@ -123,7 +121,6 @@ config SPL_SYS_ICACHE_OFF
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
@ -136,14 +133,12 @@ config SPL_SYS_DCACHE_OFF
menuconfig ARC_DBG
bool "ARC debugging"
default n
if ARC_DBG
config ARC_DBG_IOC_ENABLE
bool "Enable IO coherency unit"
depends on CPU_ARCHS38
default n
help
Enable IO coherency unit to debug problems with caches and
DMA peripherals.

3
arch/arc/include/asm/cache.h
View File

@ -16,9 +16,6 @@
*/
#define ARCH_DMA_MINALIGN 128
/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2)

30
arch/arc/lib/bootm.c
View File

@ -8,42 +8,12 @@
#include <env.h>
#include <image.h>
#include <irq_func.h>
#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp;
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
}
static int cleanup_before_linux(void)
{
disable_interrupts();

14
arch/arc/lib/cache.c
View File

@ -11,6 +11,7 @@
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <lmb.h>
#include <asm/arcregs.h>
#include <asm/arc-bcr.h>
#include <asm/cache.h>
@ -820,3 +821,16 @@ void sync_n_cleanup_cache_all(void)
__ic_entire_invalidate();
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

2
arch/arc/lib/libgcc2.h
View File

@ -35,7 +35,7 @@ typedef int HItype __attribute__ ((mode (HI)));
typedef unsigned int UHItype __attribute__ ((mode (HI)));
#if MIN_UNITS_PER_WORD > 1
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
typedef int SItype __attribute__ ((mode (SI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
#if __SIZEOF_LONG_LONG__ > 4
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */

193
arch/arm/Kconfig
View File

@ -9,9 +9,19 @@ config ARM64
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
if ARM64
config ARM64_CRC32
bool "Enable support for CRC32 instruction"
depends on ARM64
default y
help
ARMv8 implements dedicated crc32 instruction for crc32 calculation.
This is faster than software crc32 calculation. This instruction may
not be present on all ARMv8.0, but is always present on ARMv8.1 and
newer.
config POSITION_INDEPENDENT
bool "Generate position-independent pre-relocation code"
depends on ARM64 || CPU_V7A
help
U-Boot expects to be linked to a specific hard-coded address, and to
be loaded to and run from that address. This option lifts that
@ -22,6 +32,7 @@ config POSITION_INDEPENDENT
config INIT_SP_RELATIVE
bool "Specify the early stack pointer relative to the .bss section"
depends on ARM64
default n if ARCH_QEMU
default y if POSITION_INDEPENDENT
help
@ -37,6 +48,7 @@ config INIT_SP_RELATIVE
config SYS_INIT_SP_BSS_OFFSET
int "Early stack offset from the .bss base address"
depends on ARM64
depends on INIT_SP_RELATIVE
default 524288
help
@ -46,6 +58,7 @@ config SYS_INIT_SP_BSS_OFFSET
do not overlap any appended DTB.
config LINUX_KERNEL_IMAGE_HEADER
depends on ARM64
bool
help
Place a Linux kernel image header at the start of the U-Boot binary.
@ -54,14 +67,18 @@ config LINUX_KERNEL_IMAGE_HEADER
image header reports the amount of memory (BSS and similar) that
U-Boot needs to use, but which isn't part of the binary.
if LINUX_KERNEL_IMAGE_HEADER
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
depends on LINUX_KERNEL_IMAGE_HEADER
hex
help
The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
TEXT_OFFSET value written to the Linux kernel image header.
endif
endif
config GICV2
bool
config GICV3
bool
config GIC_V3_ITS
bool "ARM GICV3 ITS"
@ -104,7 +121,6 @@ config THUMB2_KERNEL
config SYS_ICACHE_OFF
bool "Do not enable icache"
default n
help
Do not enable instruction cache in U-Boot.
@ -117,7 +133,6 @@ config SPL_SYS_ICACHE_OFF
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
@ -332,21 +347,6 @@ config SYS_ARM_ARCH
default 4 if CPU_SA1100
default 8 if ARM64
config SYS_CACHE_SHIFT_5
bool
config SYS_CACHE_SHIFT_6
bool
config SYS_CACHE_SHIFT_7
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
@ -452,12 +452,11 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
config ARM_CORTEX_CPU_IS_UP
bool
default n
config USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy"
default y
depends on !ARM64
default y if !ARM64
depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
@ -466,7 +465,7 @@ config USE_ARCH_MEMCPY
config SPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for SPL"
default y if USE_ARCH_MEMCPY
depends on !ARM64 && SPL
depends on SPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
@ -475,16 +474,43 @@ config SPL_USE_ARCH_MEMCPY
config TPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for TPL"
default y if USE_ARCH_MEMCPY
depends on !ARM64 && TPL
depends on TPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove" if !ARM64
default USE_ARCH_MEMCPY if ARM64
depends on ARM64
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
default SPL_USE_ARCH_MEMCPY if ARM64
depends on SPL && ARM64
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
default TPL_USE_ARCH_MEMCPY if ARM64
depends on TPL && ARM64
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
default y
depends on !ARM64
default y if !ARM64
depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
@ -493,7 +519,7 @@ config USE_ARCH_MEMSET
config SPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for SPL"
default y if USE_ARCH_MEMSET
depends on !ARM64 && SPL
depends on SPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
@ -502,7 +528,7 @@ config SPL_USE_ARCH_MEMSET
config TPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for TPL"
default y if USE_ARCH_MEMSET
depends on !ARM64 && TPL
depends on TPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
@ -525,11 +551,6 @@ config ARCH_AT91
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
@ -579,11 +600,6 @@ config TARGET_STV0991
select SPI_FLASH
imply CMD_DM
config TARGET_FLEA3
bool "Support flea3"
select CPU_ARM1136
select GPIO_EXTRA_HEADER
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
@ -626,6 +642,11 @@ config ARCH_BCMSTB
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
select PL011_SERIAL
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
@ -723,6 +744,7 @@ config ARCH_KEYSTONE
bool "TI Keystone"
select CMD_POWEROFF
select CPU_V7A
select DDR_SPD
select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select SYS_ARCH_TIMER
@ -787,6 +809,7 @@ config ARCH_IMX8
select ARM64
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
select OF_CONTROL
select ENABLE_ARM_SOC_BOOT0_HOOK
@ -794,9 +817,11 @@ config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
select DM
select SUPPORT_SPL
imply CMD_DM
@ -805,6 +830,7 @@ config ARCH_IMX8ULP
bool "NXP i.MX8ULP platform"
select ARM64
select DM
select MACH_IMX
select OF_CONTROL
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
@ -816,6 +842,7 @@ config ARCH_IMXRT
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
select MACH_IMX
select SUPPORT_SPL
imply CMD_DM
@ -823,31 +850,29 @@ config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
select PL011_SERIAL
select SUPPORT_SPL
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
imply MXC_GPIO
config ARCH_MX28
bool "NXP i.MX28 family"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
select MACH_IMX
select SUPPORT_SPL
config ARCH_MX31
bool "NXP i.MX31 family"
select CPU_ARM1136
select GPIO_EXTRA_HEADER
select MACH_IMX
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@ -860,6 +885,7 @@ config ARCH_MX7
select ARCH_MISC_INIT
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@ -871,6 +897,7 @@ config ARCH_MX6
bool "Freescale MX6"
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@ -887,6 +914,7 @@ config ARCH_MX5
select BOARD_EARLY_INIT_F
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
imply MXC_GPIO
config ARCH_NEXELL
@ -952,6 +980,7 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
@ -962,7 +991,7 @@ config ARCH_SOCFPGA
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_SERIAL_SUPPORT
select SPL_SERIAL
select SPL_SYSRESET
select SPL_WATCHDOG
select SUPPORT_SPL
@ -982,11 +1011,11 @@ config ARCH_SOCFPGA
imply SPL_DM_SPI
imply SPL_DM_SPI_FLASH
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_MMC
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
imply SPL_SPI
imply L2X0_CACHE
config ARCH_SUNXI
@ -1032,9 +1061,9 @@ config ARCH_SUNXI
imply SPL_GPIO
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT if MMC
imply SPL_MMC if MMC
imply SPL_POWER
imply SPL_SERIAL_SUPPORT
imply SPL_SERIAL
imply USB_GADGET
config ARCH_U8500
@ -1044,14 +1073,22 @@ config ARCH_U8500
select DM_GPIO
select DM_MMC if MMC
select DM_SERIAL
select DM_USB_GADGET if DM_USB
select OF_CONTROL
select SYSRESET
select TIMER
imply AB8500_USB_PHY
imply ARM_PL180_MMCI
imply CLK
imply DM_PMIC
imply DM_RTC
imply NOMADIK_GPIO
imply NOMADIK_MTU_TIMER
imply PHY
imply PL01X_SERIAL
imply PMIC_AB8500
imply RTC_PL031
imply SYS_THUMB_BUILD
imply SYSRESET_SYSCON
config ARCH_VERSAL
@ -1062,6 +1099,7 @@ config ARCH_VERSAL
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select GICV3
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SOC_DEVICE
@ -1072,6 +1110,7 @@ config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
imply MTD_RAW_NAND
@ -1131,6 +1170,7 @@ config ARCH_ZYNQMP
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select FIRMWARE
select GICV2
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
@ -1880,6 +1920,7 @@ config TARGET_DURIAN
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
select GICV2
config TARGET_XENGUEST_ARM64
bool "Xen guest ARM64"
@ -1891,13 +1932,56 @@ config TARGET_XENGUEST_ARM64
select SSCANF
endchoice
config SUPPORT_PASSING_ATAGS
bool "Support pre-devicetree ATAG-based booting"
depends on !ARM64
imply SETUP_MEMORY_TAGS
help
Support for booting older Linux kernels, using ATAGs rather than
passing a devicetree. This is option is rarely used, and the
semantics are defined at
https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
config SETUP_MEMORY_TAGS
bool "Pass memory size information via ATAG"
depends on SUPPORT_PASSING_ATAGS
config CMDLINE_TAG
bool "Pass Linux kernel cmdline via ATAG"
depends on SUPPORT_PASSING_ATAGS
config INITRD_TAG
bool "Pass initrd starting point and size via ATAG"
depends on SUPPORT_PASSING_ATAGS
config REVISION_TAG
bool "Pass system revision via ATAG"
depends on SUPPORT_PASSING_ATAGS
config SERIAL_TAG
bool "Pass system serial number via ATAG"
depends on SUPPORT_PASSING_ATAGS
config STATIC_MACH_TYPE
bool "Statically define the Machine ID number"
help
When booting via ATAGs, enable this option if we know the correct
machine ID number to use at compile time. Some systems will be
passed the number dynamically by whatever loads U-Boot.
config MACH_TYPE
int "Machine ID number"
depends on STATIC_MACH_TYPE
help
When booting via ATAGs, the machine type must be passed as a number.
For the full list see https://www.arm.linux.org.uk/developer/machines
config ARCH_SUPPORT_TFABOOT
bool
config TFABOOT
bool "Support for booting from TF-A"
depends on ARCH_SUPPORT_TFABOOT
default n
help
Some platforms support the setup of secure registers (for instance
for CPU errata handling) or provide secure services like PSCI.
@ -1966,8 +2050,6 @@ source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
source "arch/arm/mach-imx/mx3/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
@ -2048,10 +2130,9 @@ source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
source "board/broadcom/bcm963158/Kconfig"

6
arch/arm/Makefile
View File

@ -18,7 +18,11 @@ arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7))
arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
ifeq ($(CONFIG_ARM64_CRC32),y)
arch-$(CONFIG_ARM64) =-march=armv8-a+crc
else
arch-$(CONFIG_ARM64) =-march=armv8-a
endif
# On Tegra systems we must build SPL for the armv4 core on the device
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
@ -107,7 +111,7 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
libs-y += arch/arm/mach-imx/
endif
else

5
arch/arm/config.mk
View File

@ -25,6 +25,7 @@ endif
PLATFORM_RELFLAGS += -fno-common -ffixed-r9
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mgeneral-regs-only) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
# LLVM support
@ -158,7 +159,8 @@ ifdef CONFIG_EFI_LOADER
OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
endif
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_MACH_IMX
ifneq ($(CONFIG_IMX_CONFIG),"")
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
INPUTS-y += SPL
@ -174,6 +176,7 @@ ifneq ($(CONFIG_VF610),)
INPUTS-y += u-boot.vyb
endif
endif
endif
EFI_LDS := elf_arm_efi.lds
EFI_CRT0 := crt0_arm_efi.o

1
arch/arm/cpu/arm1136/Makefile
View File

@ -7,4 +7,3 @@ extra-y = start.o
obj-y += ../arm11/
obj-$(CONFIG_MX31) += mx31/
obj-$(CONFIG_MX35) += mx35/

11
arch/arm/cpu/arm1136/mx35/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
obj-y += relocate.o

530
arch/arm/cpu/arm1136/mx35/generic.c
View File

@ -1,530 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
#include <spl.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
#define CLK_CODE_PATH(c) ((c) & 0xFF)
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
static int g_clk_mux_auto[8] = {
CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
};
static int g_clk_mux_consumer[16] = {
CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
-1, -1, CLK_CODE(4, 2, 0), -1,
};
static int hsp_div_table[3][16] = {
{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
};
u32 get_cpu_rev(void)
{
int reg;
struct iim_regs *iim =
(struct iim_regs *)IIM_BASE_ADDR;
reg = readl(&iim->iim_srev);
if (!reg) {
reg = readw(ROMPATCH_REV);
reg <<= 4;
} else {
reg += CHIP_REV_1_0;
}
return 0x35000 + (reg & 0xFF);
}
static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
{
int *pclk_mux;
if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
pclk_mux = g_clk_mux_consumer +
((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
} else {
pclk_mux = g_clk_mux_auto +
((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
}
if ((*pclk_mux) == -1)
return -1;
if (fi && fd) {
if (!CLK_CODE_PATH(*pclk_mux)) {
*fi = *fd = 1;
return CLK_CODE_ARM(*pclk_mux);
}
if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
*fi = 3;
*fd = 4;
} else {
*fi = 2;
*fd = 3;
}
}
return CLK_CODE_ARM(*pclk_mux);
}
static int get_ahb_div(u32 pdr0)
{
int *pclk_mux;
pclk_mux = g_clk_mux_consumer +
((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
if ((*pclk_mux) == -1)
return -1;
return CLK_CODE_AHB(*pclk_mux);
}
static u32 decode_pll(u32 reg, u32 infreq)
{
u32 mfi = (reg >> 10) & 0xf;
s32 mfn = reg & 0x3ff;
u32 mfd = (reg >> 16) & 0x3ff;
u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
mfd * pd);
}
static u32 get_mcu_main_clk(void)
{
u32 arm_div = 0, fi = 0, fd = 0;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
return fi / (arm_div * fd);
}
static u32 get_ipg_clk(void)
{
u32 freq = get_mcu_main_clk();
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr0 = readl(&ccm->pdr0);
return freq / (get_ahb_div(pdr0) * 2);
}
static u32 get_ipg_per_clk(void)
{
u32 freq = get_mcu_main_clk();
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr0 = readl(&ccm->pdr0);
u32 pdr4 = readl(&ccm->pdr4);
u32 div;
if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
div = CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
} else {
div = CCM_GET_DIVIDER(pdr0,
MXC_CCM_PDR0_PER_PODF_MASK,
MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
div *= get_ahb_div(pdr0);
}
return freq / div;
}
u32 imx_get_uartclk(void)
{
u32 freq;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr4 = readl(&ccm->pdr4);
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
freq = get_mcu_main_clk();
else
freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
return freq;
}
unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
{
u32 nfc_pdf, hsp_podf;
u32 pll, ret_val = 0, usb_podf;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 reg = readl(&ccm->pdr0);
u32 reg4 = readl(&ccm->pdr4);
reg |= 0x1;
switch (clk) {
case CPU_CLK:
ret_val = get_mcu_main_clk();
break;
case AHB_CLK:
ret_val = get_mcu_main_clk();
break;
case HSP_CLK:
if (reg & CLKMODE_CONSUMER) {
hsp_podf = (reg >> 20) & 0x3;
pll = get_mcu_main_clk();
hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
if (hsp_podf > 0) {
ret_val = pll / hsp_podf;
} else {
puts("mismatch HSP with ARM clock setting\n");
ret_val = 0;
}
} else {
ret_val = get_mcu_main_clk();
}
break;
case IPG_CLK:
ret_val = get_ipg_clk();
break;
case IPG_PER_CLK:
ret_val = get_ipg_per_clk();
break;
case NFC_CLK:
nfc_pdf = (reg4 >> 28) & 0xF;
pll = get_mcu_main_clk();
/* AHB/nfc_pdf */
ret_val = pll / (nfc_pdf + 1);
break;
case USB_CLK:
usb_podf = (reg4 >> 22) & 0x3F;
if (reg4 & 0x200)
pll = get_mcu_main_clk();
else
pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
ret_val = pll / (usb_podf + 1);
break;
default:
printf("Unknown clock: %d\n", clk);
break;
}
return ret_val;
}
unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
{
u32 ret_val = 0, pdf, pre_pdf, clk_sel;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 mpdr2 = readl(&ccm->pdr2);
u32 mpdr3 = readl(&ccm->pdr3);
u32 mpdr4 = readl(&ccm->pdr4);
switch (clk) {
case UART1_BAUD:
case UART2_BAUD:
case UART3_BAUD:
clk_sel = mpdr3 & (1 << 14);
pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
pdf = mpdr2 & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case SSI2_BAUD:
pre_pdf = (mpdr2 >> 27) & 0x7;
pdf = (mpdr2 >> 8) & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
clk_sel = (pre_pdf & 0x80);
pdf = (pre_pdf >> 22) & 0x3F;
pre_pdf = (pre_pdf >> 28) & 0x7;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case ESDHC1_CLK:
clk_sel = mpdr3 & 0x40;
pdf = mpdr3 & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC2_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 8) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC3_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SPDIF_CLK:
clk_sel = mpdr3 & 0x400000;
pre_pdf = (mpdr3 >> 29) & 0x7;
pdf = (mpdr3 >> 23) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
printf("%s(): This clock: %d not supported yet\n",
__func__, clk);
break;
}
return ret_val;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_AHB_CLK:
break;
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return imx_get_uartclk();
case MXC_ESDHC1_CLK:
return mxc_get_peri_clock(ESDHC1_CLK);
case MXC_ESDHC2_CLK:
return mxc_get_peri_clock(ESDHC2_CLK);
case MXC_ESDHC3_CLK:
return mxc_get_peri_clock(ESDHC3_CLK);
case MXC_USB_CLK:
return mxc_get_main_clock(USB_CLK);
case MXC_FEC_CLK:
return get_ipg_clk();
case MXC_CSPI_CLK:
return get_ipg_clk();
}
return -1;
}
#ifdef CONFIG_FEC_MXC
/*
* The MX35 has no fuse for MAC, return a NULL MAC
*/
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
memset(mac, 0, 6);
}
u32 imx_get_fecclk(void)
{
return mxc_get_clock(MXC_IPG_CLK);
}
#endif
int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
u32 cpufreq = get_mcu_main_clk();
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
printf("ipg clock : %dHz\n", get_ipg_clk());
printf("ipg per clock : %dHz\n", get_ipg_per_clk());
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
return 0;
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks",
""
);
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 cause = readl(&ccm->rcsr) & 0x0F;
switch (cause) {
case 0x0000:
return "POR";
case 0x0002:
return "JTAG";
case 0x0004:
return "RST";
case 0x0008:
return "WDOG";
default:
return "unknown reset";
}
}
int print_cpuinfo(void)
{
u32 srev = get_cpu_rev();
printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
(srev & 0xF0) >> 4, (srev & 0x0F),
get_mcu_main_clk() / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
}
#define RCSR_MEM_CTL_WEIM 0
#define RCSR_MEM_CTL_NAND 1
#define RCSR_MEM_CTL_ATA 2
#define RCSR_MEM_CTL_EXPANSION 3
#define RCSR_MEM_TYPE_NOR 0
#define RCSR_MEM_TYPE_ONENAND 2
#define RCSR_MEM_TYPE_SD 0
#define RCSR_MEM_TYPE_I2C 2
#define RCSR_MEM_TYPE_SPI 3
u32 spl_boot_device(void)
{
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 rcsr = readl(&ccm->rcsr);
u32 mem_type, mem_ctl;
/* In external mode, no boot device is returned */
if ((rcsr >> 10) & 0x03)
return BOOT_DEVICE_NONE;
mem_ctl = (rcsr >> 25) & 0x03;
mem_type = (rcsr >> 23) & 0x03;
switch (mem_ctl) {
case RCSR_MEM_CTL_WEIM:
switch (mem_type) {
case RCSR_MEM_TYPE_NOR:
return BOOT_DEVICE_NOR;
case RCSR_MEM_TYPE_ONENAND:
return BOOT_DEVICE_ONENAND;
default:
return BOOT_DEVICE_NONE;
}
case RCSR_MEM_CTL_NAND:
return BOOT_DEVICE_NAND;
case RCSR_MEM_CTL_EXPANSION:
switch (mem_type) {
case RCSR_MEM_TYPE_SD:
return BOOT_DEVICE_MMC1;
case RCSR_MEM_TYPE_I2C:
return BOOT_DEVICE_I2C;
case RCSR_MEM_TYPE_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_NONE;
}
}
return BOOT_DEVICE_NONE;
}

120
arch/arm/cpu/arm1136/mx35/mx35_sdram.c
View File

@ -1,120 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <linux/types.h>
#include <asm/arch/sys_proto.h>
#define ESDCTL_DDR2_EMR2 0x04000000
#define ESDCTL_DDR2_EMR3 0x06000000
#define ESDCTL_PRECHARGE 0x00000400
#define ESDCTL_DDR2_EN_DLL 0x02000400
#define ESDCTL_DDR2_RESET_DLL 0x00000333
#define ESDCTL_DDR2_MR 0x00000233
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
enum {
SMODE_NORMAL = 0,
SMODE_PRECHARGE,
SMODE_AUTO_REFRESH,
SMODE_LOAD_REG,
SMODE_MANUAL_REFRESH
};
#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
static inline void dram_wait(unsigned int count)
{
volatile unsigned int wait = count;
while (wait--)
;
}
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
u32 row, u32 col, u32 dsize, u32 refresh)
{
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
u32 *cfg_reg, *ctl_reg;
u32 val;
u32 ctlval;
switch (start_address) {
case CSD0_BASE_ADDR:
cfg_reg = &esdc->esdcfg0;
ctl_reg = &esdc->esdctl0;
break;
case CSD1_BASE_ADDR:
cfg_reg = &esdc->esdcfg1;
ctl_reg = &esdc->esdctl1;
break;
default:
return;
}
/* The MX35 supports 11 up to 14 rows */
if (row < 11 || row > 14 || col < 8 || col > 10)
return;
ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
/* Initialize MISC register for DDR2 */
val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
writel(val, &esdc->esdmisc);
val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
writel(val, &esdc->esdmisc);
/*
* according to DDR2 specs, wait a while before
* the PRECHARGE_ALL command
*/
dram_wait(0x20000);
/* Load DDR2 config and timing */
writel(ddr2_config, cfg_reg);
/* Precharge ALL */
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
ctl_reg);
writel(0xda, start_address + ESDCTL_PRECHARGE);
/* Load mode */
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
ctl_reg);
writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
/* Precharge ALL */
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
ctl_reg);
writel(0xda, start_address + ESDCTL_PRECHARGE);
/* Set mode auto refresh : at least two refresh are required */
writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
ctl_reg);
writel(0xda, start_address);
writel(0xda, start_address);
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
ctl_reg);
writeb(0xda, start_address + ESDCTL_DDR2_MR);
writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
/* OCD mode exit */
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
/* Set normal mode */
writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
ctl_reg);
dram_wait(0x20000);
/* Do not set delay lines, only for MDDR */
}

22
arch/arm/cpu/arm1136/mx35/relocate.S
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX35-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The i.MX35 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

46
arch/arm/cpu/arm1136/mx35/timer.c
View File

@ -1,46 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/ptrace.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
/*
* nothing really to do with interrupts, just starts up a counter.
* The 32KHz 32-bit timer overruns in 134217 seconds
*/
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
return 0;
}

8
arch/arm/cpu/arm1136/start.S
View File

@ -39,7 +39,7 @@ reset:
msr cpsr,r0
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -62,7 +62,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -81,7 +81,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
@ -91,4 +91,4 @@ cpu_init_crit:
mov lr, ip /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

10
arch/arm/cpu/arm720t/start.S
View File

@ -37,8 +37,8 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
@ -62,8 +62,8 @@ c_runtime_cpu_setup:
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
@ -76,4 +76,4 @@ cpu_init_crit:
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

22
arch/arm/cpu/arm920t/start.S
View File

@ -35,25 +35,11 @@ reset:
orr r0, r0, #0xd3
msr cpsr, r0
#if defined(CONFIG_AT91RM9200DK)
/*
* relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
mov r2, #16
copyex:
subs r2, r2, #1
ldr r3, [r0], #4
str r3, [r1], #4
bne copyex
#endif
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -78,7 +64,7 @@ c_runtime_cpu_setup:
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -97,7 +83,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
@ -109,4 +95,4 @@ cpu_init_crit:
mov lr, ip
#endif
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

2
arch/arm/cpu/arm926ejs/Makefile
View File

@ -12,8 +12,6 @@ extra-y :=
endif
endif
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/

7
arch/arm/cpu/arm926ejs/armada100/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
obj-y = cpu.o timer.o dram.o

93
arch/arm/cpu/arm926ejs/armada100/cpu.c
View File

@ -1,93 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
#define SET_MRVL_ID (1<<8)
#define L2C_RAM_SEL (1<<4)
int arch_cpu_init(void)
{
u32 val;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID;
writel(val, &cpuregs->cpu_conf);
/* Enable Clocks for all hardware units */
writel(0xFFFFFFFF, &mpmu->acgr);
/* Turn on AIB and AIB-APB Functional clock */
writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
/* ensure L2 cache is not mapped as SRAM */
val = readl(&cpuregs->cpu_conf);
val = val & ~(L2C_RAM_SEL);
writel(val, &cpuregs->cpu_conf);
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
#ifdef CONFIG_I2C_MV
/* Enable general I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
/* Enable power I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
#endif
/*
* Enable Functional and APB clock at 14.7456MHz
* for configured UART console
*/
#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart3);
#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart2);
#else
writel(UARTCLK14745KHZ, &apb1clkres->uart1);
#endif
icache_enable();
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 id;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
id = readl(&cpuregs->chip_id);
printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
return 0;
}
#endif
#ifdef CONFIG_I2C_MV
void i2c_clk_enable(void)
{
}
#endif

117
arch/arm/cpu/arm926ejs/armada100/dram.c
View File

@ -1,117 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* ARMADA100 DRAM controller supports upto 8 banks
* for chip select 0 and 1
*/
/*
* DDR Memory Control Registers
* Refer Datasheet Appendix A.17
*/
struct armd1ddr_map_registers {
u32 cs; /* Memory Address Map Register -CS */
u32 pad[3];
};
struct armd1ddr_registers {
u8 pad[0x100 - 0x000];
struct armd1ddr_map_registers mmap[2];
};
/*
* armd1_sdram_base - reads SDRAM Base Address Register
*/
u32 armd1_sdram_base(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
return result;
}
/*
* armd1_sdram_size - reads SDRAM size
*/
u32 armd1_sdram_size(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs);
result = (result >> 16) & 0xF;
if (result < 0x7) {
printf("Unknown DRAM Size\n");
return -1;
} else {
return ((0x8 << (result - 0x7)) * 1024 * 1024);
}
}
int dram_init(void)
{
int i;
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = armd1_sdram_base(i);
gd->bd->bi_dram[i].size = armd1_sdram_size(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
if (gd->bd->bi_dram[i].start != gd->ram_size)
break;
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash */
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
/*
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
int dram_init_banksize(void)
{
dram_init();
return 0;
}

198
arch/arm/cpu/arm926ejs/armada100/timer.c
View File

@ -1,198 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#include <asm/global_data.h>
#include <linux/delay.h>
/*
* Timer registers
* Refer Section A.6 in Datasheet
*/
struct armd1tmr_registers {
u32 clk_ctrl; /* Timer clk control reg */
u32 match[9]; /* Timer match registers */
u32 count[3]; /* Timer count registers */
u32 status[3];
u32 ie[3];
u32 preload[3]; /* Timer preload value */
u32 preload_ctrl[3];
u32 wdt_match_en;
u32 wdt_match_r;
u32 wdt_val;
u32 wdt_sts;
u32 icr[3];
u32 wdt_icr;
u32 cer; /* Timer count enable reg */
u32 cmr;
u32 ilr[3];
u32 wcr;
u32 wfar;
u32 wsar;
u32 cvwr;
};
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
* register after it captures counter value.
*/
ulong read_timer(void)
{
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
volatile int loop=100;
writel(COUNT_RD_REQ, &armd1timers->cvwr);
while (loop--);
return(readl(&armd1timers->cvwr));
}
static ulong get_timer_masked(void)
{
ulong now = read_timer();
if (now >= gd->arch.tbl) {
/* normal mode */
gd->arch.tbu += now - gd->arch.tbl;
} else {
/* we have an overflow ... */
gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
}
gd->arch.tbl = now;
return gd->arch.tbu;
}
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
void __udelay(unsigned long usec)
{
ulong delayticks;
ulong endtime;
delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
endtime = get_timer_masked() + delayticks;
while (get_timer_masked() < endtime);
}
/*
* init the Timer
*/
int timer_init(void)
{
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
/* Enable Timer clock at 3.25 MHZ */
writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
/* load value into timer */
writel(0x0, &armd1timers->clk_ctrl);
/* Use Timer 0 Match Resiger 0 */
writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
/* Preload value is 0 */
writel(0x0, &armd1timers->preload[TIMER]);
/* Enable match comparator 0 for Timer 0 */
writel(0x1, &armd1timers->preload_ctrl[TIMER]);
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
/* init the gd->arch.tbu and gd->arch.tbl value */
gd->arch.tbl = read_timer();
gd->arch.tbu = 0;
return 0;
}
#define MPMU_APRR_WDTR (1<<4)
#define TMR_WFAR 0xbaba /* WDT Register First key */
#define TMP_WSAR 0xeb10 /* WDT Register Second key */
/*
* This function uses internal Watchdog Timer
* based reset mechanism.
* Steps to write watchdog registers (protected access)
* 1. Write key value to TMR_WFAR reg.
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu(void)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
u32 val;
/* negate hardware reset to the WDT after system reset */
val = readl(&mpmu->aprr);
val = val | MPMU_APRR_WDTR;
writel(val, &mpmu->aprr);
/* reset/enable WDT clock */
writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
/* clear previous WDT status */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0, &armd1timers->wdt_sts);
/* set match counter */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0xf, &armd1timers->wdt_match_r);
/* enable WDT reset */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0x3, &armd1timers->wdt_match_en);
while(1);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return (ulong)CONFIG_SYS_HZ;
}

1
arch/arm/cpu/arm926ejs/cache.c
View File

@ -89,4 +89,3 @@ void enable_caches(void)
dcache_enable();
#endif
}

274
arch/arm/cpu/arm926ejs/mx25/generic.c
View File

@ -1,274 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on mx27/generic.c:
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <clock_legacy.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
& CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
mfd * pd);
}
static ulong imx_get_mpllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
static ulong imx_get_upllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->upctl), fref);
}
static ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_mpllclk();
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
fref = lldiv((u64) fref * 3, 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
return fref / div;
}
static ulong imx_get_ahbclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_armclk();
ulong div;
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
return fref / div;
}
static ulong imx_get_ipgclk(void)
{
return imx_get_ahbclk() / 2;
}
static ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
imx_get_ahbclk();
ulong div;
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
return fref / div;
}
int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
ulong div = (fref + freq - 1) / freq;
if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
return -EINVAL;
clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
div << CCM_PERCLK_SHIFT(clk));
if (from_upll)
setbits_le32(&ccm->mcr, 1 << clk);
else
clrbits_le32(&ccm->mcr, 1 << clk);
return 0;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
if (clk >= MXC_CLK_NUM)
return -1;
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_AHB_CLK:
return imx_get_ahbclk();
case MXC_IPG_CLK:
case MXC_CSPI_CLK:
case MXC_FEC_CLK:
return imx_get_ipgclk();
default:
return imx_get_perclk(clk);
}
}
u32 get_cpu_rev(void)
{
u32 srev;
u32 system_rev = 0x25000;
/* read SREV register from IIM module */
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
srev = readl(&iim->iim_srev);
switch (srev) {
case 0x00:
system_rev |= CHIP_REV_1_0;
break;
case 0x01:
system_rev |= CHIP_REV_1_1;
break;
case 0x02:
system_rev |= CHIP_REV_1_2;
break;
default:
system_rev |= 0x8000;
break;
}
return system_rev;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 cause = readl(&ccm->rcsr) & 0x0f;
if (cause == 0)
return "POR";
else if (cause == 1)
return "RST";
else if ((cause & 2) == 2)
return "WDOG";
else if ((cause & 4) == 4)
return "SW RESET";
else if ((cause & 8) == 8)
return "JTAG";
else
return "unknown reset";
}
int print_cpuinfo(void)
{
char buf[32];
u32 cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
((cpurev & 0x8000) ? " unknown" : ""),
strmhz(buf, imx_get_armclk()));
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
#if defined(CONFIG_FEC_MXC)
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val = readl(&ccm->cgr0);
val |= (1 << 23);
writel(val, &ccm->cgr0);
return fecmxc_initialize(bis);
}
#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
}
#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
#ifdef CONFIG_FEC_MXC
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */

22
arch/arm/cpu/arm926ejs/mx25/relocate.S
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX25-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The i.MX25 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

40
arch/arm/cpu/arm926ejs/mx25/reset.c
View File

@ -1,40 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0, &regs->wcr);
/* Write Service Sequence */
writew(WSR_UNLOCK1, &regs->wsr);
writew(WSR_UNLOCK2, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1) ;
}

50
arch/arm/cpu/arm926ejs/mx25/timer.c
View File

@ -1,50 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
* Add support for MX25
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32KHz 32-bit timer overruns in 134217 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
/* setup GP Timer 1 */
writel(GPT_CTRL_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
return 0;
}

4
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View File

@ -23,7 +23,7 @@
DECLARE_GLOBAL_DATA_PTR;
static gd_t gdata __section(".data");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
#ifdef CONFIG_SPL_SERIAL
static struct bd_info bdata __section(".data");
#endif
@ -108,7 +108,7 @@ static void mxs_spl_fixup_vectors(void)
static void mxs_spl_console_init(void)
{
#ifdef CONFIG_SPL_SERIAL_SUPPORT
#ifdef CONFIG_SPL_SERIAL
gd->bd = &bdata;
gd->baudrate = CONFIG_BAUDRATE;
serial_init();

8
arch/arm/cpu/arm926ejs/start.S
View File

@ -46,7 +46,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -69,7 +69,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush D cache before disabling it
@ -100,7 +100,7 @@ flush_dcache:
#endif
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Go setup Memory and board specific bits prior to relocation.
*/
@ -109,4 +109,4 @@ flush_dcache:
mov lr, r4 /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

6
arch/arm/cpu/arm946es/start.S
View File

@ -45,7 +45,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -70,7 +70,7 @@ c_runtime_cpu_setup:
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -89,7 +89,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Go setup Memory and board specific bits prior to relocation.
*/

2
arch/arm/cpu/armv7/Makefile
View File

@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif

1
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -20,6 +20,7 @@ config ARCH_LS1021A
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_I2C_MXC
imply CMD_PCI
imply SCSI
imply SCSI_AHCI

4
arch/arm/cpu/armv7/ls102xa/clock.c
View File

@ -42,8 +42,8 @@ void get_sys_info(struct sys_info *sys_info)
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif

2
arch/arm/cpu/armv7/ls102xa/spl.c
View File

@ -8,7 +8,7 @@
u32 spl_boot_device(void)
{
#ifdef CONFIG_SPL_MMC_SUPPORT
#ifdef CONFIG_SPL_MMC
return BOOT_DEVICE_MMC1;
#endif
return BOOT_DEVICE_NAND;

1
arch/arm/cpu/armv7/psci-common.c
View File

@ -43,4 +43,3 @@ u32 __secure psci_get_context_id(int cpu)
{
return psci_context_id[cpu];
}

51
arch/arm/cpu/armv7/start.S
View File

@ -39,6 +39,42 @@ reset:
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
#ifdef CONFIG_POSITION_INDEPENDENT
/*
* Fix .rela.dyn relocations. This allows U-Boot to loaded to and
* executed at a different address than it was linked at.
*/
pie_fixup:
adr r0, reset /* r0 <- Runtime value of reset label */
ldr r1, =reset /* r1 <- Linked value of reset label */
subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */
beq pie_fixup_done
adr r0, pie_fixup
ldr r1, _rel_dyn_start_ofs
add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */
ldr r1, _rel_dyn_end_ofs
add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */
pie_fix_loop:
ldr r0, [r2] /* r0 <- Link location */
ldr r1, [r2, #4] /* r1 <- fixup */
cmp r1, #23 /* relative fixup? */
bne pie_skip_reloc
/* relative fix: increase location by offset */
add r0, r4
ldr r1, [r0]
add r1, r4
str r1, [r0]
str r0, [r2]
add r2, #8
pie_skip_reloc:
cmp r2, r3
blo pie_fix_loop
pie_fixup_done:
#endif
#ifdef CONFIG_ARMV7_LPAE
/*
* check for Hypervisor support
@ -80,11 +116,11 @@ switch_to_hypervisor_ret:
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#ifdef CONFIG_CPU_V7A
bl cpu_init_cp15
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
#endif
@ -320,8 +356,8 @@ skip_errata_801819:
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers
@ -340,3 +376,10 @@ ENTRY(cpu_init_crit)
b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
#if CONFIG_POSITION_INDEPENDENT
_rel_dyn_start_ofs:
.word __rel_dyn_start - pie_fixup
_rel_dyn_end_ofs:
.word __rel_dyn_end - pie_fixup
#endif

3
arch/arm/cpu/armv8/Kconfig
View File

@ -3,7 +3,6 @@ if ARM64
config ARMV8_SPL_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
depends on SPL
default n
help
The default exception vector table is only used for the crash
dump, but still takes quite a lot of space in the image size.
@ -128,7 +127,6 @@ config PSCI_RESET
config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
default n
help
PSCI is Power State Coordination Interface defined by ARM.
The PSCI in U-boot provides a general framework and each platform
@ -156,7 +154,6 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
config ARMV8_EA_EL3_FIRST
bool "External aborts and SError interrupt exception are taken in EL3"
default n
help
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.

19
arch/arm/cpu/armv8/cache.S
View File

@ -27,13 +27,11 @@ ENTRY(__asm_dcache_level)
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
clz w5, w3 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
@ -72,8 +70,7 @@ ENTRY(__asm_dcache_all)
mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
lsr x11, x10, #24
and x11, x11, #0x7 /* x11 <- loc */
ubfx x11, x10, #24, #3 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
@ -83,8 +80,7 @@ ENTRY(__asm_dcache_all)
/* x15 <- return address */
loop_level:
lsl x12, x0, #1
add x12, x12, x0 /* x0 <- tripled cache level */
add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
lsr x12, x10, x12
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
@ -131,8 +127,7 @@ ENDPROC(__asm_invalidate_dcache_all)
.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
lsr x3, x3, #16
and x3, x3, #0xf
ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */
@ -158,7 +153,7 @@ ENDPROC(__asm_flush_dcache_range)
.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
ubfm x3, x3, #16, #19
ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */

20
arch/arm/cpu/armv8/fel_utils.S
View File

@ -64,18 +64,18 @@ ENTRY(return_to_fel)
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
.word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
.word 0xe5901008 // ldr r1, [r0, #8]
.word 0xe129f001 // msr CPSR_fc, r1
.word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
.word 0xe5901008 // ldr r1, [r0, #8]
.word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
.word 0xe590d000 // ldr sp, [r0]
.word 0xe590e004 // ldr lr, [r0, #4]
.word 0xe5901010 // ldr r1, [r0, #16]
.word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
.word 0xe590100c // ldr r1, [r0, #12]
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xe590d000 // ldr sp, [r0]
.word 0xe590e004 // ldr lr, [r0, #4]
.word 0xe5901010 // ldr r1, [r0, #16]
.word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
.word 0xe590100c // ldr r1, [r0, #12]
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
.word 0xe12fff1e // bx lr ; return to FEL
.word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)

25
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -4,6 +4,8 @@ config ARCH_LS1012A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
@ -25,6 +27,7 @@ config ARCH_LS1028A
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
@ -58,7 +61,9 @@ config ARCH_LS1043A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -84,13 +89,16 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply CMD_PCI
imply ID_EEPROM
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -117,8 +125,10 @@ config ARCH_LS1046A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply ID_EEPROM
imply SCSI
imply SCSI_AHCI
imply SPL_SYS_I2C_LEGACY
config ARCH_LS1088A
bool
@ -126,6 +136,8 @@ config ARCH_LS1088A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -158,7 +170,9 @@ config ARCH_LS1088A
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
imply ID_EEPROM
imply SCSI
imply SPL_SYS_I2C_LEGACY
imply PANIC_HANG
config ARCH_LS2080A
@ -170,6 +184,8 @@ config ARCH_LS2080A
select ARM_ERRATA_833471
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -210,12 +226,15 @@ config ARCH_LS2080A
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
imply ID_EEPROM
imply PANIC_HANG
imply SPL_SYS_I2C_LEGACY
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
@ -242,11 +261,13 @@ config ARCH_LX2162A
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
imply SPL_SYS_I2C_LEGACY
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
@ -272,12 +293,15 @@ config ARCH_LX2160A
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
imply ID_EEPROM
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
imply SPL_SYS_I2C_LEGACY
config FSL_LSCH2
bool
select SKIP_LOWLEVEL_INIT
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
@ -429,7 +453,6 @@ config QSPI_AHB_INIT
config FSPI_AHB_EN_4BYTE
bool "Enable 4-byte Fast Read command for AHB mode"
default n
help
The default setting for FlexSPI AHB bus just supports 3-byte addressing.
But some FlexSPI flash sizes are up to 64MBytes.

2
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1147,7 +1147,7 @@ int arch_early_init_r(void)
#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
* configured via both serdes(sgmii, xfi, xlaui etc) bits and via
* configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits

36
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
View File

@ -42,22 +42,22 @@ Flash Layout
pre-silicon platforms (simulator and emulator):
-------------------------
| FIT Image |
| FIT Image |
| (linux + DTB + RFS) |
------------------------- ----> 0x0120_0000
| Debug Server FW |
| Debug Server FW |
------------------------- ----> 0x00C0_0000
| AIOP FW |
| AIOP FW |
------------------------- ----> 0x0070_0000
| MC FW |
| MC FW |
------------------------- ----> 0x006C_0000
| MC DPL Blob |
| MC DPL Blob |
------------------------- ----> 0x0020_0000
| BootLoader + Env|
| BootLoader + Env|
------------------------- ----> 0x0000_1000
| PBI |
| PBI |
------------------------- ----> 0x0000_0080
| RCW |
| RCW |
------------------------- ----> 0x0000_0000
32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@ -70,45 +70,45 @@ Flash Layout
----------------------------------------- ----> 0x5_8790_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8510_0000 |
| PHY firmware (2M) | |
| PHY firmware (2M) | |
----------------------------------------- ----> 0x5_84F0_0000 | 64K
| Debug Server FW (2M) | | Alt
----------------------------------------- ----> 0x5_84D0_0000 | Bank
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8490_0000 (vbank4)
| MC DPC Blob (1M) | |
| MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8480_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8470_0000 |
| MC FW (4M) | |
| MC FW (4M) | |
----------------------------------------- ----> 0x5_8430_0000 |
| BootLoader Environment (1M) | |
| BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8420_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8410_0000 |
| RCW and PBI (1M) | |
| RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8400_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8390_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8110_0000 |
| PHY firmware (2M) | |
| PHY firmware (2M) | |
----------------------------------------- ----> 0x5_80F0_0000 | 64K
| Debug Server FW (2M) | | Bank
----------------------------------------- ----> 0x5_80D0_0000 |
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8090_0000 (vbank0)
| MC DPC Blob (1M) | |
| MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8080_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8070_0000 |
| MC FW (4M) | |
| MC FW (4M) | |
----------------------------------------- ----> 0x5_8030_0000 |
| BootLoader Environment (1M) | |
| BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8020_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8010_0000 |
| RCW and PBI (1M) | |
| RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8000_0000 ---
128-MB NOR flash layout for QDS and RDB boards

8
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
View File

@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- Up to 1 x XFI supporting 10G interface
- Up to 1 x 10GBase-R supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
- Two PLLs per four-lane SerDes
- Support for 10G operation
- Ethernet interfaces by FMan
- Up to 2 x XFI supporting 10G interface (MAC 9, 10)
- Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
Single WRIOP tile supporting 130Gbps using 18 MACs
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
Support for XFI (and 10GBase-KR)
Support for 10GBase-R (and 10GBase-KR)
Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
Ethernet interfaces
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
Support for XFI (and 10GBase-KR)
Support for 10GBase-R (and 10GBase-KR)
Support for CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.

4
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -61,8 +61,8 @@ void get_sys_info(struct sys_info *sys_info)
#endif
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif

6
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
View File

@ -78,10 +78,10 @@ void get_sys_info(struct sys_info *sys_info)
void *offset;
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
sys_info->freq_ddrbus = get_board_ddr_clk();
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
sys_info->freq_ddrbus2 = get_board_ddr_clk();
#endif
#else
sys_info->freq_ddrbus = sysclk;

4
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -250,7 +250,7 @@ ENTRY(lowlevel_init)
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders.
* placeholders.
*/
.macro tzasc_prog, xreg
@ -259,7 +259,7 @@ ENTRY(lowlevel_init)
mov x16, #0x10000
mul x14, \xreg, x16
add x14, x14,x12
mov x1, #0x8
mov x1, #0x8
add x1, x1, x14
ldr w0, [x1] /* Filter 0 Gate Keeper Register */

2
arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
View File

@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/*
* LS1044A/1048A support only one XFI port
* LS1044A/1048A support only one 10GBase-R port
* Disable MAC1 for LS1044A/1048A
*/
if (serdes == FSL_SRDS_1 && lane == 2) {

2
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -329,7 +329,7 @@ static void erratum_rcw_src(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
#ifdef CONFIG_SYS_I2C_LEGACY
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
u8 __iomem *ptr;
#ifdef I2C1_BASE_ADDR
ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);

2
arch/arm/cpu/armv8/fsl-layerscape/spintable.S
View File

@ -93,7 +93,7 @@ __secondary_boot_func:
4:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
switch_el x7, _dead_loop, 0f, _dead_loop
0: armv8_switch_to_el1_m x4, x6, x7
0: armv8_switch_to_el1_m x4, x6, x7, x9
#else
switch_el x7, 0f, _dead_loop, _dead_loop
0: armv8_switch_to_el2_m x4, x6, x7

4
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
#ifdef CONFIG_SPL_MMC_SUPPORT
#ifdef CONFIG_SPL_MMC
return BOOT_DEVICE_MMC1;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
@ -88,7 +88,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
spl_set_bd();
#ifdef CONFIG_SYS_I2C_LEGACY
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
#ifdef CONFIG_SPL_I2C
i2c_init_all();
#endif

2
arch/arm/cpu/armv8/hisilicon/pinmux.c
View File

@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral)
return 0;
}

2
arch/arm/cpu/armv8/transition.S
View File

@ -40,7 +40,7 @@ ENTRY(armv8_switch_to_el1)
* now, jump to the address saved in x4.
*/
br x4
1: armv8_switch_to_el1_m x4, x5, x6
1: armv8_switch_to_el1_m x4, x5, x6, x7
ENDPROC(armv8_switch_to_el1)
.popsection

1
arch/arm/cpu/armv8/xen/hypercall.S
View File

@ -76,4 +76,3 @@ HYPERCALL2(sched_op);
HYPERCALL2(event_channel_op);
HYPERCALL2(hvm_op);
HYPERCALL2(memory_op);

6
arch/arm/cpu/pxa/start.S
View File

@ -45,7 +45,7 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -92,7 +92,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -111,7 +111,7 @@ cpu_init_crit:
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
/*
* Enable MMU to use DCache as DRAM.

4
arch/arm/cpu/sa1100/start.S
View File

@ -39,7 +39,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -95,7 +95,7 @@ cpu_init_crit:
ldr r1, cpuspeed
str r1, [r0, #PPCR]
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will

13
arch/arm/dts/Makefile
View File

@ -929,7 +929,7 @@ endif
dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach-u-boot.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
keystone-k2g-evm.dtb \
@ -1090,7 +1090,14 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_AM6) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
k3-am65-iot2050-spl.dtb \
k3-am6528-iot2050-basic.dtb \
k3-am6528-iot2050-basic-pg2.dtb \
k3-am6548-iot2050-advanced.dtb \
k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
@ -1120,6 +1127,8 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb

4
arch/arm/dts/ast2600.dtsi
View File

@ -474,21 +474,25 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
status = "disabled";
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
status = "disabled";
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
status = "disabled";
};
wdt4: watchdog@1e7850C0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";
};
lpc: lpc@1e789000 {

4
arch/arm/dts/at91-sama5d27_som1_ek.dts
View File

@ -68,7 +68,7 @@
};
ahb {
usb1: ohci@00400000 {
usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 42 0>;
pinctrl-names = "default";
@ -76,7 +76,7 @@
status = "okay";
};
usb2: ehci@00500000 {
usb2: ehci@500000 {
status = "okay";
};

31
arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi
View File

@ -13,6 +13,30 @@
};
};
&pinctrl_mikrobus1_uart {
u-boot,dm-pre-reloc;
};
&pinctrl_qspi1_sck_cs_default {
u-boot,dm-pre-reloc;
};
&pinctrl_qspi1_dat_default {
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_default {
u-boot,dm-pre-reloc;
};
&qspi1 {
u-boot,dm-pre-reloc;
flash@0 {
u-boot,dm-pre-reloc;
};
};
&sdmmc0 {
u-boot,dm-pre-reloc;
};
@ -21,10 +45,3 @@
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_default {
u-boot,dm-pre-reloc;
};
&pinctrl_mikrobus1_uart {
u-boot,dm-pre-reloc;
};

48
arch/arm/dts/at91-sama5d2_icp.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board
* SAMA5D2 Industrial Connectivity Board
* SAMA5D2 Industrial Connectivity Platform
*
* Copyright (c) 2018, Microchip Technology Inc.
* 2018, Eugen Hristev <eugen.hristev@microchip.com>
@ -33,10 +33,19 @@
};
apb {
uart0: serial@f801c000 { /* mikrobus1 uart */
qspi1: spi@f0024000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_uart>;
pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <83000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
macb0: ethernet@f8008000 {
@ -46,6 +55,12 @@
status = "okay";
};
uart0: serial@f801c000 { /* mikrobus1 uart */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_uart>;
status = "okay";
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
@ -70,6 +85,7 @@
pagesize = <16>;
};
};
pioA: gpio@fc038000 {
status = "okay";
pinctrl {
@ -109,6 +125,26 @@
bias-pull-up;
};
pinctrl_mikrobus1_uart: mikrobus1_uart {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
pinmux = <PIN_PA6__QSPI1_SCK>,
<PIN_PA11__QSPI1_CS>;
bias-disable;
};
pinctrl_qspi1_dat_default: qspi1_dat_default {
pinmux = <PIN_PA7__QSPI1_IO0>,
<PIN_PA8__QSPI1_IO1>,
<PIN_PA9__QSPI1_IO2>,
<PIN_PA10__QSPI1_IO3>;
bias-pull-up;
};
pinctrl_sdmmc0_default: sdmmc0_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
@ -119,12 +155,6 @@
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_mikrobus1_uart: mikrobus1_uart {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
};
};
};

4
arch/arm/dts/at91-sama5d2_ptc_ek.dts
View File

@ -76,7 +76,7 @@
status = "okay";
};
usb1: ohci@00400000 {
usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PB12 GPIO_ACTIVE_HIGH
@ -87,7 +87,7 @@
status = "okay";
};
usb2: ehci@00500000 {
usb2: ehci@500000 {
status = "okay";
};

8
arch/arm/dts/at91-sama5d2_xplained.dts
View File

@ -12,6 +12,10 @@
stdout-path = &uart1;
};
memory {
reg = <0x20000000 0x20000000>;
};
onewire_tm: onewire {
gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@ -25,7 +29,7 @@
};
ahb {
usb1: ohci@00400000 {
usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 42 0>;
pinctrl-names = "default";
@ -33,7 +37,7 @@
status = "okay";
};
usb2: ehci@00500000 {
usb2: ehci@500000 {
status = "okay";
};

2
arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

4
arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
@ -14,6 +14,6 @@
&enetc0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

10
arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
@ -30,25 +30,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

6
arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
&slot1 {
@ -19,13 +19,13 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

2
arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*
*/

2
arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

4
arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
&slot2 {
@ -19,7 +19,7 @@
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
&slot3 {
@ -19,7 +19,7 @@
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};

4
arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
View File

@ -9,12 +9,12 @@
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac4 {

4
arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
View File

@ -9,10 +9,10 @@
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};

16
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
View File

@ -9,40 +9,40 @@
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};

16
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
View File

@ -24,49 +24,49 @@
&dpmac1 {
status = "okay";
phy-handle = <&mdio1_phy1>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-handle = <&mdio1_phy2>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-handle = <&mdio1_phy3>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-handle = <&mdio1_phy4>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-handle = <&mdio2_phy1>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-handle = <&mdio2_phy2>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-handle = <&mdio2_phy3>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-handle = <&mdio2_phy4>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&emdio1 {

2
arch/arm/dts/fsl-sch-24801.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device tree fragment for RCW SCH-24801 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-sch-28021.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device tree fragment for RCW SCH-28021 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

4
arch/arm/dts/fsl-sch-30841.dtsi
View File

@ -2,14 +2,14 @@
/*
* Device tree fragment for RCW SCH-30841 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
* It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
* It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/

4
arch/arm/dts/fsl-sch-30842.dtsi
View File

@ -2,13 +2,13 @@
/*
* Device tree fragment for RCW SCH-30842 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
* SGMII-2500, USXGMII, XFI.
* 2500base-x, USXGMII, 10GBase-R.
* PHY address is 0x02.
*/
phy@02 {

447
arch/arm/dts/k3-am64-main.dtsi
View File

@ -5,6 +5,17 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
/ {
serdes_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
@ -26,6 +37,20 @@
};
};
main_conf: syscon@43000000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x0 0x43000000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x43000000 0x20000>;
serdes_ln_ctrl: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@ -50,12 +75,12 @@
};
};
dmss: dmss {
dmss: bus@48000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
ti,sci-dev-id = <25>;
@ -142,7 +167,7 @@
};
};
dmsc: dmsc@44043000 {
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@ -156,7 +181,7 @@
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
@ -197,8 +222,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -210,8 +233,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -223,8 +244,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -236,8 +255,6 @@
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -249,8 +266,6 @@
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -262,8 +277,6 @@
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -275,8 +288,6 @@
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -381,6 +392,52 @@
clocks = <&k3_clks 145 0>;
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <3>;
ti,interrupt-ranges = <0 32 16>;
};
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <190>, <191>, <192>,
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <87>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
};
main_gpio1: gpio@601000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <88>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
};
sdhci0: mmc@fa10000 {
compatible = "ti,am64-sdhci-8bit";
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
@ -451,7 +508,8 @@
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 de ad be ef];
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&main_conf 0x200>;
};
cpsw_port2: port@2 {
@ -459,7 +517,7 @@
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 01 de ad be ef];
mac-address = [00 00 00 00 00 00];
};
};
@ -485,30 +543,23 @@
};
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
<77 1 IRQ_TYPE_EDGE_RISING>,
<77 2 IRQ_TYPE_EDGE_RISING>,
<77 3 IRQ_TYPE_EDGE_RISING>,
<77 4 IRQ_TYPE_EDGE_RISING>,
<77 5 IRQ_TYPE_EDGE_RISING>,
<77 6 IRQ_TYPE_EDGE_RISING>,
<77 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
cpts@39000000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x39000000 0x0 0x400>;
reg-names = "cpts";
power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 84 0>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 84 0>;
assigned-clock-parents = <&k3_clks 84 8>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
usbss0: cdns-usb@f900000{
compatible = "ti,am64-usb", "ti,j721e-usb";
compatible = "ti,am64-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
@ -537,69 +588,275 @@
};
};
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
<78 1 IRQ_TYPE_EDGE_RISING>,
<78 2 IRQ_TYPE_EDGE_RISING>,
<78 3 IRQ_TYPE_EDGE_RISING>,
<78 4 IRQ_TYPE_EDGE_RISING>,
<78 5 IRQ_TYPE_EDGE_RISING>,
<78 6 IRQ_TYPE_EDGE_RISING>,
<78 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
tscadc0: tscadc@28001000 {
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
reg = <0x00 0x28001000 0x00 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 0 0>;
assigned-clocks = <&k3_clks 0 0>;
assigned-clock-parents = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
adc {
#io-channel-cells = <1>;
compatible = "ti,am654-adc", "ti,am3359-adc";
};
};
main_i2c0: i2c@20000000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x0 0x20000000 0x0 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 102 2>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
fss: bus@fc00000 {
compatible = "simple-bus";
reg = <0x00 0x0fc00000 0x00 0x70000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ospi0: spi@fc40000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&k3_clks 75 6>;
assigned-clocks = <&k3_clks 75 6>;
assigned-clock-parents = <&k3_clks 75 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
};
};
main_i2c1: i2c@20010000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x0 0x20010000 0x0 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 103 2>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
#hwlock-cells = <1>;
};
main_i2c2: i2c@20020000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20020000 0x0 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 104 2>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
mailbox0_cluster2: mailbox@29020000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29020000 0x00 0x200>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
main_i2c3: i2c@20030000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20030000 0x0 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
mailbox0_cluster3: mailbox@29030000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29030000 0x00 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster4: mailbox@29040000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29040000 0x00 0x200>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster5: mailbox@29050000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29050000 0x00 0x200>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster6: mailbox@29060000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29060000 0x00 0x200>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
mailbox0_cluster7: mailbox@29070000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29070000 0x00 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
main_r5fss0: r5fss@78000000 {
compatible = "ti,am64-r5fss";
ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0x78000000 0x00 0x78000000 0x10000>,
<0x78100000 0x00 0x78100000 0x10000>,
<0x78200000 0x00 0x78200000 0x08000>,
<0x78300000 0x00 0x78300000 0x08000>;
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@78000000 {
compatible = "ti,am64-r5f";
reg = <0x78000000 0x00010000>,
<0x78100000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <121>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 121 1>;
firmware-name = "am64-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@78200000 {
compatible = "ti,am64-r5f";
reg = <0x78200000 0x00008000>,
<0x78300000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <122>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 122 1>;
firmware-name = "am64-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@78400000 {
compatible = "ti,am64-r5fss";
ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x78400000 0x00 0x78400000 0x10000>,
<0x78500000 0x00 0x78500000 0x10000>,
<0x78600000 0x00 0x78600000 0x08000>,
<0x78700000 0x00 0x78700000 0x08000>;
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
main_r5fss1_core0: r5f@78400000 {
compatible = "ti,am64-r5f";
reg = <0x78400000 0x00010000>,
<0x78500000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <123>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 123 1>;
firmware-name = "am64-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@78600000 {
compatible = "ti,am64-r5f";
reg = <0x78600000 0x00008000>,
<0x78700000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <124>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 124 1>;
firmware-name = "am64-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
serdes_wiz0: wiz@f000000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
num-lanes = <1>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
assigned-clocks = <&k3_clks 162 1>;
assigned-clock-parents = <&k3_clks 162 5>;
serdes0: serdes@f000000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x0f000000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 162 1>,
<&k3_clks 162 1>,
<&k3_clks 162 1>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
};
};
pcie0_rc: pcie@f102000 {
compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x68000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
max-link-speed = <2>;
num-lanes = <1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
vendor-id = <0x104c>;
device-id = <0xb010>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
};
pcie0_ep: pcie-ep@f102000 {
compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x68000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
max-link-speed = <2>;
num-lanes = <1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fck";
clocks = <&k3_clks 105 2>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
max-functions = /bits/ 8 <1>;
};
};

32
arch/arm/dts/k3-am64-mcu.dtsi
View File

@ -9,8 +9,6 @@
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -22,8 +20,6 @@
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@ -73,4 +69,32 @@
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
};
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x4201000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <23>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
};

2
arch/arm/dts/k3-am64.dtsi
View File

@ -28,8 +28,6 @@
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};

259
arch/arm/dts/k3-am642-evm.dts
View File

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
@ -36,6 +38,60 @@
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: fixedregulator-evm12v0 {
@ -154,6 +210,15 @@
>;
};
main_spi0_pins_default: main-spi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@ -207,6 +272,22 @@
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
};
&main_uart0 {
@ -285,6 +366,11 @@
};
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_i2c0 {
status = "disabled";
};
@ -301,28 +387,16 @@
status = "disabled";
};
&cpsw3g {
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <16>;
};
};
@ -355,3 +429,148 @@
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};

299
arch/arm/dts/k3-am642-sk.dts
View File

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
@ -35,6 +37,93 @@
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
vusb_main: fixed-regulator-vusb-main5v0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vusb_main>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc_3v3_sys>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
};
@ -52,6 +141,12 @@
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@ -99,6 +194,30 @@
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
};
&mcu_uart0 {
status = "disabled";
};
&mcu_uart1 {
status = "disabled";
};
&main_uart1 {
@ -126,8 +245,51 @@
status = "disabled";
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"PRU_DETECT", "MMC1_SD_EN",
"VPP_LDO_EN", "RPI_PS_3V3_En",
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
};
};
&main_i2c3 {
status = "disabled";
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
@ -135,6 +297,33 @@
disable-wp;
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_USB>;
};
&serdes0 {
serdes0_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 1>;
};
};
&usbss0 {
ti,vbus-divider;
};
&usb0 {
dr_mode = "host";
maximum-speed = "super-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
@ -147,10 +336,120 @@
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&tscadc0 {
status = "disabled";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&pcie0_rc {
status = "disabled";
};
&pcie0_ep {
status = "disabled";
};

173
arch/arm/dts/k3-am65-iot2050-boot-image.dtsi Normal file
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@ -0,0 +1,173 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2020-2021
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
* Chao Zeng <chao.zeng@siemens.com>
*/
#include <config.h>
/ {
binman {
filename = "flash.bin";
pad-byte = <0xff>;
size = <0x8c0000>;
blob-ext@0x000000 {
offset = <0x000000>;
filename = "tiboot3.bin";
};
blob@0x080000 {
offset = <0x080000>;
filename = "tispl.bin";
};
fit@0x280000 {
description = "U-Boot for IOT2050";
offset = <0x280000>;
images {
u-boot {
description = "U-Boot";
type = "standalone";
arch = "arm64";
os = "u-boot";
compression = "none";
load = <0x80800000>;
entry = <0x80800000>;
u-boot-nodtb {
};
};
fdt-iot2050-basic {
description = "k3-am6528-iot2050-basic.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6528-iot2050-basic.dtb";
};
};
fdt-iot2050-basic-pg2 {
description = "k3-am6528-iot2050-basic-pg2.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb";
};
};
fdt-iot2050-advanced {
description = "k3-am6548-iot2050-advanced.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6548-iot2050-advanced.dtb";
};
};
fdt-iot2050-advanced-pg2 {
description = "k3-am6548-iot2050-advanced-pg2.dtb";
type = "flat_dt";
arch = "arm64";
compression = "none";
blob {
filename = "arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb";
};
};
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
k3-rti-wdt-firmware {
type = "firmware";
load = <0x82000000>;
arch = "arm";
compression = "none";
blob-ext {
filename = CONFIG_WDT_K3_RTI_FW_FILE;
missing-msg = "k3-rti-wdt-firmware";
};
};
#endif
};
configurations {
default = "conf-iot2050-basic";
conf-iot2050-basic {
description = "iot2050-basic";
firmware = "u-boot";
fdt = "fdt-iot2050-basic";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
conf-iot2050-basic-pg2 {
description = "iot2050-basic-pg2";
firmware = "u-boot";
fdt = "fdt-iot2050-basic-pg2";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
conf-iot2050-advanced {
description = "iot2050-advanced";
firmware = "u-boot";
fdt = "fdt-iot2050-advanced";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
conf-iot2050-advanced-pg2 {
description = "iot2050-advanced-pg2";
firmware = "u-boot";
fdt = "fdt-iot2050-advanced-pg2";
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
loadables = "k3-rti-wdt-firmware";
#endif
};
};
};
/* primary env */
fill@0x680000 {
offset = <0x680000>;
size = <0x020000>;
fill-byte = [00];
};
/* secondary env */
fill@0x6a0000 {
offset = <0x6a0000>;
size = <0x020000>;
fill-byte = [00];
};
/* PG1 sysfw, basic variant */
blob-ext@0x6c0000 {
offset = <0x6c0000>;
filename = "sysfw.itb";
};
/* PG1 sysfw, advanced variant */
blob-ext@0x740000 {
offset = <0x740000>;
filename = "sysfw.itb_HS";
};
/* PG2 sysfw, basic variant */
blob-ext@0x7c0000 {
offset = <0x7c0000>;
filename = "sysfw_sr2.itb";
};
/* PG2 sysfw, advanced variant */
blob-ext@0x840000 {
offset = <0x840000>;
filename = "sysfw_sr2.itb_HS";
};
};
};

46
arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi Normal file
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@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2021
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Basic and Advanced variants, PG1
*/
&dss {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
};
&serdes0 {
status = "disabled";
};
&sdhci1 {
no-1-8-v;
};
&tx_pru0_0 {
status = "disabled";
};
&tx_pru0_1 {
status = "disabled";
};
&tx_pru1_0 {
status = "disabled";
};
&tx_pru1_1 {
status = "disabled";
};
&tx_pru2_0 {
status = "disabled";
};
&tx_pru2_1 {
status = "disabled";
};

51
arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi Normal file
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@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2021
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common bits of the IOT2050 Basic and Advanced variants, PG2
*/
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-pin-default {
pinctrl-single,pins = <
/* (AF12) GPIO1_24, used as cp2102 reset */
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
>;
};
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&cp2102n_reset_pin_default>;
gpio-line-names =
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "CP2102N-RESET";
};
&dss {
/* Workaround needed to get DP clock of 154Mhz */
assigned-clocks = <&k3_clks 67 0>;
};
&serdes0 {
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
};
&dwc3_0 {
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
phys = <&serdes0 PHY_TYPE_USB3 0>;
phy-names = "usb3-phy";
};
&usb0_phy {
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};

99
arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi Normal file
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@ -0,0 +1,99 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* Common U-Boot bits of the IOT2050 Basic and Advanced variants
*/
/ {
aliases {
spi0 = &ospi0;
};
leds {
u-boot,dm-spl;
status-led-red {
u-boot,dm-spl;
};
status-led-green {
u-boot,dm-spl;
};
};
};
&cbass_mcu {
u-boot,dm-spl;
};
&cbass_wakeup {
u-boot,dm-spl;
};
&cbass_main {
u-boot,dm-spl;
main-navss {
u-boot,dm-spl;
};
};
&wkup_pmx0 {
u-boot,dm-spl;
mcu-fss0-ospi0-pins-default {
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main-uart1-pins-default {
u-boot,dm-spl;
};
};
&main_uart1 {
u-boot,dm-spl;
current-speed = <115200>;
};
&wkup_gpio0 {
u-boot,dm-spl;
};
&ospi0 {
u-boot,dm-spl;
flash@0 {
u-boot,dm-spl;
};
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
u-boot,dm-spl;
};
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&fss {
u-boot,dm-spl;
};

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