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Merge git://git.denx.de/u-boot into x1

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Conflicts:

	drivers/usb/usb_ohci.c
This commit is contained in:
Markus Klotzbuecher
2008-10-21 09:18:01 +02:00
parent 9dbc366744 f82642e338
commit 50bd0057ba
2127 changed files with 61411 additions and 55335 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
cpu/74xx_7xx/cache.S
View File

@@ -52,7 +52,7 @@ _GLOBAL(invalidate_l1_data_cache)
/*
* Flush data cache.
*/
_GLOBAL(flush_data_cache)
_GLOBAL(flush_dcache)
lis r3,0
lis r5,CACHE_LINE_SIZE
flush:
@@ -292,7 +292,7 @@ _GLOBAL(dcache_enable)
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
#ifdef CFG_L2
#ifdef CONFIG_SYS_L2
mflr r5
bl l2cache_enable /* uses r3 and r4 */
sync
@@ -303,12 +303,12 @@ _GLOBAL(dcache_enable)
/*
* Disable data cache(s) - L1 and optionally L2
* Calls flush_data_cache and l2cache_disable_no_flush.
* Calls flush_dcache and l2cache_disable_no_flush.
* LR saved in r4
*/
_GLOBAL(dcache_disable)
mflr r4 /* save link register */
bl flush_data_cache /* uses r3 and r5 */
bl flush_dcache /* uses r3 and r5 */
sync
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
@@ -318,7 +318,7 @@ _GLOBAL(dcache_disable)
andc r3, r3, r5 /* no enable, no invalidate */
mtspr HID0, r3
sync
#ifdef CFG_L2
#ifdef CONFIG_SYS_L2
bl l2cache_disable_no_flush /* uses r3 */
#endif
mtlr r4 /* restore link register */
@@ -389,11 +389,11 @@ _GLOBAL(l2cache_enable)
/*
* Disable L2 cache
* Calls flush_data_cache. LR is saved in r4
* Calls flush_dcache. LR is saved in r4
*/
_GLOBAL(l2cache_disable)
mflr r4 /* save link register */
bl flush_data_cache /* uses r3 and r5 */
bl flush_dcache /* uses r3 and r5 */
sync
mtlr r4 /* restore link register */
l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */

20
cpu/74xx_7xx/cpu.c
View File

@@ -256,16 +256,16 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
__asm__ __volatile__ ("isync");
__asm__ __volatile__ ("sync");
#ifdef CFG_RESET_ADDRESS
addr = CFG_RESET_ADDRESS;
#ifdef CONFIG_SYS_RESET_ADDRESS
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
* note: when CFG_MONITOR_BASE points to a RAM address,
* CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
* address. Better pick an address known to be invalid on your
* system and assign it to CFG_RESET_ADDRESS.
* system and assign it to CONFIG_SYS_RESET_ADDRESS.
*/
addr = CFG_MONITOR_BASE - sizeof (ulong);
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
soft_restart(addr);
while(1); /* not reached */
@@ -277,18 +277,18 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* For the 7400 the TB clock runs at 1/4 the cpu bus speed.
*/
#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SYS_CONFIG_BUS_CLK)
unsigned long get_tbclk(void)
{
return (gd->bus_clk / 4);
}
#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
#else /* ! CONFIG_AMIGAONEG3SE and !CONFIG_SYS_CONFIG_BUS_CLK*/
unsigned long get_tbclk (void)
{
return CFG_BUS_HZ / 4;
return CONFIG_SYS_BUS_HZ / 4;
}
#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
#endif /* CONFIG_AMIGAONEG3SE or CONFIG_SYS_CONFIG_BUS_CLK*/
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)

2
cpu/74xx_7xx/interrupts.c
View File

@@ -48,7 +48,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER));
puts("interrupt_init: setting decrementer_count\n");
#endif
*decrementer_count = get_tbclk() / CFG_HZ;
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
return (0);
}

10
cpu/74xx_7xx/kgdb.S
View File

@@ -43,7 +43,7 @@ kgdb_flush_cache_all:
addis r4,r0,0x0040
kgdb_flush_loop:
lwz r5,0(r3)
addi r3,r3,CFG_CACHELINE_SIZE
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
cmp 0,0,r3,r4
bne kgdb_flush_loop
SYNC
@@ -55,21 +55,21 @@ kgdb_flush_loop:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
li r5,CFG_CACHELINE_SIZE-1
li r5,CONFIG_SYS_CACHELINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,CFG_CACHELINE_SHIFT
srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
addi r3,r3,CFG_CACHELINE_SIZE
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
addi r6,r6,CFG_CACHELINE_SIZE
addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
bdnz 2b
SYNC
blr

4
cpu/74xx_7xx/speed.c
View File

@@ -127,8 +127,8 @@ int get_clocks (void)
{
ulong clock = 0;
#ifdef CFG_BUS_CLK
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
#ifdef CONFIG_SYS_BUS_CLK
gd->bus_clk = CONFIG_SYS_BUS_CLK; /* bus clock is a fixed frequency */
#else
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#endif

176
cpu/74xx_7xx/start.S
View File

@@ -209,7 +209,7 @@ boot_warm:
bl invalidate_bats
sync
#ifdef CFG_L2
#ifdef CONFIG_SYS_L2
/* init the L2 cache */
addis r3, r0, L2_INIT@h
ori r3, r3, L2_INIT@l
@@ -225,12 +225,12 @@ boot_warm:
*/
#endif
#ifdef CFG_L2
#ifdef CONFIG_SYS_L2
/* invalidate the L2 cache */
bl l2cache_invalidate
sync
#endif
#ifdef CFG_BOARD_ASM_INIT
#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* do early init */
bl board_asm_init
#endif
@@ -238,8 +238,8 @@ boot_warm:
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
lis r3, CFG_MONITOR_BASE@h
ori r3, r3, CFG_MONITOR_BASE@l
lis r3, CONFIG_SYS_MONITOR_BASE@h
ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -280,15 +280,15 @@ in_flash:
bl l1dcache_enable
sync
#endif
#ifdef CFG_INIT_RAM_LOCK
#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
/* set up the stack pointer in our newly created
* cache-ram (r1) */
lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -343,146 +343,146 @@ setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
addis r4, r0, CFG_IBAT0L@h
ori r4, r4, CFG_IBAT0L@l
addis r3, r0, CFG_IBAT0U@h
ori r3, r3, CFG_IBAT0U@l
addis r4, r0, CONFIG_SYS_IBAT0L@h
ori r4, r4, CONFIG_SYS_IBAT0L@l
addis r3, r0, CONFIG_SYS_IBAT0U@h
ori r3, r3, CONFIG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
isync
/* DBAT 0 */
addis r4, r0, CFG_DBAT0L@h
ori r4, r4, CFG_DBAT0L@l
addis r3, r0, CFG_DBAT0U@h
ori r3, r3, CFG_DBAT0U@l
addis r4, r0, CONFIG_SYS_DBAT0L@h
ori r4, r4, CONFIG_SYS_DBAT0L@l
addis r3, r0, CONFIG_SYS_DBAT0U@h
ori r3, r3, CONFIG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
isync
/* IBAT 1 */
addis r4, r0, CFG_IBAT1L@h
ori r4, r4, CFG_IBAT1L@l
addis r3, r0, CFG_IBAT1U@h
ori r3, r3, CFG_IBAT1U@l
addis r4, r0, CONFIG_SYS_IBAT1L@h
ori r4, r4, CONFIG_SYS_IBAT1L@l
addis r3, r0, CONFIG_SYS_IBAT1U@h
ori r3, r3, CONFIG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
isync
/* DBAT 1 */
addis r4, r0, CFG_DBAT1L@h
ori r4, r4, CFG_DBAT1L@l
addis r3, r0, CFG_DBAT1U@h
ori r3, r3, CFG_DBAT1U@l
addis r4, r0, CONFIG_SYS_DBAT1L@h
ori r4, r4, CONFIG_SYS_DBAT1L@l
addis r3, r0, CONFIG_SYS_DBAT1U@h
ori r3, r3, CONFIG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
isync
/* IBAT 2 */
addis r4, r0, CFG_IBAT2L@h
ori r4, r4, CFG_IBAT2L@l
addis r3, r0, CFG_IBAT2U@h
ori r3, r3, CFG_IBAT2U@l
addis r4, r0, CONFIG_SYS_IBAT2L@h
ori r4, r4, CONFIG_SYS_IBAT2L@l
addis r3, r0, CONFIG_SYS_IBAT2U@h
ori r3, r3, CONFIG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
isync
/* DBAT 2 */
addis r4, r0, CFG_DBAT2L@h
ori r4, r4, CFG_DBAT2L@l
addis r3, r0, CFG_DBAT2U@h
ori r3, r3, CFG_DBAT2U@l
addis r4, r0, CONFIG_SYS_DBAT2L@h
ori r4, r4, CONFIG_SYS_DBAT2L@l
addis r3, r0, CONFIG_SYS_DBAT2U@h
ori r3, r3, CONFIG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
isync
/* IBAT 3 */
addis r4, r0, CFG_IBAT3L@h
ori r4, r4, CFG_IBAT3L@l
addis r3, r0, CFG_IBAT3U@h
ori r3, r3, CFG_IBAT3U@l
addis r4, r0, CONFIG_SYS_IBAT3L@h
ori r4, r4, CONFIG_SYS_IBAT3L@l
addis r3, r0, CONFIG_SYS_IBAT3U@h
ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
isync
/* DBAT 3 */
addis r4, r0, CFG_DBAT3L@h
ori r4, r4, CFG_DBAT3L@l
addis r3, r0, CFG_DBAT3U@h
ori r3, r3, CFG_DBAT3U@l
addis r4, r0, CONFIG_SYS_DBAT3L@h
ori r4, r4, CONFIG_SYS_DBAT3L@l
addis r3, r0, CONFIG_SYS_DBAT3U@h
ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
isync
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
addis r4, r0, CFG_IBAT4L@h
ori r4, r4, CFG_IBAT4L@l
addis r3, r0, CFG_IBAT4U@h
ori r3, r3, CFG_IBAT4U@l
addis r4, r0, CONFIG_SYS_IBAT4L@h
ori r4, r4, CONFIG_SYS_IBAT4L@l
addis r3, r0, CONFIG_SYS_IBAT4U@h
ori r3, r3, CONFIG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
isync
/* DBAT 4 */
addis r4, r0, CFG_DBAT4L@h
ori r4, r4, CFG_DBAT4L@l
addis r3, r0, CFG_DBAT4U@h
ori r3, r3, CFG_DBAT4U@l
addis r4, r0, CONFIG_SYS_DBAT4L@h
ori r4, r4, CONFIG_SYS_DBAT4L@l
addis r3, r0, CONFIG_SYS_DBAT4U@h
ori r3, r3, CONFIG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
isync
/* IBAT 5 */
addis r4, r0, CFG_IBAT5L@h
ori r4, r4, CFG_IBAT5L@l
addis r3, r0, CFG_IBAT5U@h
ori r3, r3, CFG_IBAT5U@l
addis r4, r0, CONFIG_SYS_IBAT5L@h
ori r4, r4, CONFIG_SYS_IBAT5L@l
addis r3, r0, CONFIG_SYS_IBAT5U@h
ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync
/* DBAT 5 */
addis r4, r0, CFG_DBAT5L@h
ori r4, r4, CFG_DBAT5L@l
addis r3, r0, CFG_DBAT5U@h
ori r3, r3, CFG_DBAT5U@l
addis r4, r0, CONFIG_SYS_DBAT5L@h
ori r4, r4, CONFIG_SYS_DBAT5L@l
addis r3, r0, CONFIG_SYS_DBAT5U@h
ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
addis r4, r0, CFG_IBAT6L@h
ori r4, r4, CFG_IBAT6L@l
addis r3, r0, CFG_IBAT6U@h
ori r3, r3, CFG_IBAT6U@l
addis r4, r0, CONFIG_SYS_IBAT6L@h
ori r4, r4, CONFIG_SYS_IBAT6L@l
addis r3, r0, CONFIG_SYS_IBAT6U@h
ori r3, r3, CONFIG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
addis r4, r0, CFG_DBAT6L@h
ori r4, r4, CFG_DBAT6L@l
addis r3, r0, CFG_DBAT6U@h
ori r3, r3, CFG_DBAT6U@l
addis r4, r0, CONFIG_SYS_DBAT6L@h
ori r4, r4, CONFIG_SYS_DBAT6L@l
addis r3, r0, CONFIG_SYS_DBAT6U@h
ori r3, r3, CONFIG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
/* IBAT 7 */
addis r4, r0, CFG_IBAT7L@h
ori r4, r4, CFG_IBAT7L@l
addis r3, r0, CFG_IBAT7U@h
ori r3, r3, CFG_IBAT7U@l
addis r4, r0, CONFIG_SYS_IBAT7L@h
ori r4, r4, CONFIG_SYS_IBAT7L@l
addis r3, r0, CONFIG_SYS_IBAT7U@h
ori r3, r3, CONFIG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
isync
/* DBAT 7 */
addis r4, r0, CFG_DBAT7L@h
ori r4, r4, CFG_DBAT7L@l
addis r3, r0, CFG_DBAT7U@h
ori r3, r3, CFG_DBAT7U@l
addis r4, r0, CONFIG_SYS_DBAT7L@h
ori r4, r4, CONFIG_SYS_DBAT7L@l
addis r3, r0, CONFIG_SYS_DBAT7U@h
ori r3, r3, CONFIG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
isync
@@ -612,16 +612,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
lis r4, CFG_MONITOR_BASE@h /* Source Address */
ori r4, r4, CFG_MONITOR_BASE@l
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
@@ -639,11 +639,11 @@ relocate_code:
bl board_relocate_rom
sync
mr r3, r10 /* Destination Address */
lis r4, CFG_MONITOR_BASE@h /* Source Address */
ori r4, r4, CFG_MONITOR_BASE@l
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
#else
cmplw cr1,r3,r4
addi r0,r5,3
@@ -851,14 +851,14 @@ trap_reloc:
blr
#ifdef CFG_INIT_RAM_LOCK
#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
li r2, ((CFG_INIT_RAM_END & ~31) + \
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r2
1:
dcbz r0, r3
@@ -876,10 +876,10 @@ lock_ram_in_cache:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
li r2, ((CFG_INIT_RAM_END & ~31) + \
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r2
1: icbi r0, r3
addi r3, r3, 32

2
cpu/arm1136/cpu.c
View File

@@ -89,7 +89,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

75
cpu/arm1136/mx31/interrupts.c
View File

@@ -27,30 +27,49 @@
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
/* General purpose timers registers */
#define GPTCR __REG(TIMER_BASE) /* Control register */
#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
#define GPTCR __REG(TIMER_BASE) /* Control register */
#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
#define TICK_TO_TIME(t) ((t) * CONFIG_SYS_HZ / CONFIG_MX31_CLK32)
#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CONFIG_SYS_HZ)
#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \
999999) / 1000000)
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME)
#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME)
#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK)
#endif
static ulong timestamp;
static ulong lastinc;
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int interrupt_init (void)
{
int i;
/* setup GP Timer 1 */
GPTCR = GPTCR_SWR;
for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */
for (i = 0; i < 100; i++)
GPTCR = 0; /* We have no udelay by now */
GPTPR = 0; /* 32Khz */
GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
/* Freerun Mode, PERCLK1 input */
GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
return 0;
}
@@ -67,7 +86,7 @@ void reset_timer(void)
reset_timer_masked();
}
ulong get_timer_masked (void)
unsigned long long get_ticks (void)
{
ulong now = GPTCNT; /* current tick value */
@@ -80,6 +99,17 @@ ulong get_timer_masked (void)
return timestamp;
}
ulong get_timer_masked (void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return TICK_TO_TIME(get_ticks());
}
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
@@ -87,29 +117,20 @@ ulong get_timer (ulong base)
void set_timer (ulong t)
{
timestamp = TIME_TO_TICK(t);
}
/* delay x useconds AND perserve advance timstamp value */
void udelay (unsigned long usec)
{
ulong tmo, tmp;
unsigned long long tmp;
ulong tmo;
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
tmo = US_TO_TICK(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
tmp = get_timer (0); /* get current timestamp */
if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
else
tmo += tmp; /* else, set advancing stamp wake up time */
while (get_timer_masked () < tmo)/* loop till event */
/*NOP*/;
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
void reset_cpu (ulong addr)

12
cpu/arm1136/mx31/serial.c
View File

@@ -25,18 +25,18 @@
#define __REG(x) (*((volatile u32 *)(x)))
#ifdef CFG_MX31_UART1
#ifdef CONFIG_SYS_MX31_UART1
#define UART_PHYS 0x43f90000
#elif defined(CFG_MX31_UART2)
#elif defined(CONFIG_SYS_MX31_UART2)
#define UART_PHYS 0x43f94000
#elif defined(CFG_MX31_UART3)
#elif defined(CONFIG_SYS_MX31_UART3)
#define UART_PHYS 0x5000c000
#elif defined(CFG_MX31_UART4)
#elif defined(CONFIG_SYS_MX31_UART4)
#define UART_PHYS 0x43fb0000
#elif defined(CFG_MX31_UART5)
#elif defined(CONFIG_SYS_MX31_UART5)
#define UART_PHYS 0x43fb4000
#else
#error "define CFG_MX31_UARTx to use the mx31 UART driver"
#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
#endif
/* Register definitions */

18
cpu/arm1136/omap24xx/interrupts.c
View File

@@ -37,7 +37,7 @@
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
#define READ_TIMER (*((volatile ulong *)(CFG_TIMERBASE+TCRR)))
#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
static ulong timestamp;
static ulong lastinc;
@@ -48,9 +48,9 @@ int interrupt_init (void)
int32_t val;
/* Start the counter ticking up */
*((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
*((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */
reset_timer_masked(); /* init the timestamp and lastinc value */
@@ -81,10 +81,10 @@ void udelay (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -125,10 +125,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
endtime = get_timer_masked () + tmo;
@@ -154,6 +154,6 @@ unsigned long long get_ticks(void)
ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

16
cpu/arm1136/start.S
View File

@@ -178,8 +178,8 @@ stack_setup:
#ifdef CONFIG_ONENAND_IPL
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -290,8 +290,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -323,8 +323,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
@@ -341,8 +341,8 @@ cpu_init_crit:
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
ldr r0, _armboot_start @ get data regions start
sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool
sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack

4
cpu/arm1176/s3c64xx/interrupts.c
View File

@@ -150,7 +150,7 @@ void reset_timer(void)
ulong get_timer_masked(void)
{
unsigned long long res = get_ticks();
do_div (res, (timer_load_val / (100 * CFG_HZ)));
do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
return res;
}
@@ -161,7 +161,7 @@ ulong get_timer(ulong base)
void set_timer(ulong t)
{
timestamp = t * (timer_load_val / (100 * CFG_HZ));
timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
}
void udelay(unsigned long usec)

26
cpu/arm1176/start.S
View File

@@ -37,8 +37,8 @@
#endif
#include <s3c6400.h>
#if !defined(CONFIG_ENABLE_MMU) && !defined(CFG_PHY_UBOOT_BASE)
#define CFG_PHY_UBOOT_BASE CFG_UBOOT_BASE
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
/*
@@ -105,7 +105,7 @@ _TEXT_BASE:
* by scsuh.
*/
_TEXT_PHY_BASE:
.word CFG_PHY_UBOOT_BASE
.word CONFIG_SYS_PHY_UBOOT_BASE
.globl _armboot_start
_armboot_start:
@@ -209,7 +209,7 @@ enable_mmu:
/* Set the TTB register */
ldr r0, _mmu_table_base
ldr r1, =CFG_PHY_UBOOT_BASE
ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
ldr r2, =0xfff00000
bic r0, r0, r2
orr r1, r0, r1
@@ -242,11 +242,11 @@ skip_hw_init:
/* Set up the stack */
stack_setup:
#ifdef CONFIG_MEMORY_UPPER_CODE
ldr sp, =(CFG_UBOOT_BASE + CFG_UBOOT_SIZE - 0xc)
ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc)
#else
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
#endif
@@ -357,9 +357,9 @@ phy_last_jump:
stmia sp, {r0 - r12}
ldr r2, _armboot_start
sub r2, r2, #(CFG_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
/* set base 2 words into abort stack */
sub r2, r2, #(CFG_GBL_DATA_SIZE+8)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
@@ -377,9 +377,9 @@ phy_last_jump:
/* setup our mode stack (enter in banked mode) */
ldr r13, _armboot_start
/* move past malloc pool */
sub r13, r13, #(CFG_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
/* move to reserved a couple spots for abort stack */
sub r13, r13, #(CFG_GBL_DATA_SIZE + 8)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
/* save caller lr in position 0 of saved stack */
str lr, [r13]
@@ -407,9 +407,9 @@ phy_last_jump:
/* get data regions start */
ldr r0, _armboot_start
/* move past malloc pool */
sub r0, r0, #(CFG_MALLOC_LEN)
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
/* move past gbl and a couple spots for abort stack */
sub r0, r0, #(CFG_GBL_DATA_SIZE + 8)
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */

2
cpu/arm720t/cpu.c
View File

@@ -41,7 +41,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

18
cpu/arm720t/interrupts.c
View File

@@ -95,7 +95,7 @@ static void timer_isr( void *data) {
unsigned int *pTime = (unsigned int *)data;
(*pTime)++;
if ( !(*pTime % (CFG_HZ/4))) {
if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
/* toggle LED 0 */
PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
}
@@ -118,7 +118,7 @@ int interrupt_init (void)
IRQEN = 0;
/* operate timer 2 in non-prescale mode */
TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
NETARM_GEN_TCTL_ENABLE |
NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
@@ -166,9 +166,9 @@ int interrupt_init (void)
/*
* Load Timer data register with count down value.
* count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
* count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
*/
PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
/*
* Enable global interrupt
@@ -181,7 +181,7 @@ int interrupt_init (void)
#elif defined(CONFIG_LPC2292)
PUT32(T0IR, 0); /* disable all timer0 interrupts */
PUT32(T0TCR, 0); /* disable timer0 */
PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
PUT32(T0MCR, 0);
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
@@ -223,7 +223,7 @@ void udelay (unsigned long usec)
ulong tmo;
tmo = usec / 1000;
tmo *= CFG_HZ;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
tmo += get_timer (0);
@@ -268,10 +268,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CFG_HZ;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -294,7 +294,7 @@ void udelay (unsigned long usec)
{
u32 ticks;
ticks = (usec * CFG_HZ) / 1000000;
ticks = (usec * CONFIG_SYS_HZ) / 1000000;
ticks += get_timer (0);

4
cpu/arm720t/lpc2292/flash.c
View File

@@ -85,7 +85,7 @@ int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
command[1] = flash_addr;
command[2] = COPY_BUFFER_LOCATION;
command[3] = 512;
command[4] = CFG_SYS_CLK_FREQ >> 10;
command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP copy failed\n");
@@ -132,7 +132,7 @@ int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
command[0] = IAP_CMD_ERASE;
command[1] = s_first;
command[2] = s_last;
command[3] = CFG_SYS_CLK_FREQ >> 10;
command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP erase failed\n");

2
cpu/arm720t/serial.c
View File

@@ -85,7 +85,7 @@ void serial_putc (const char c)
if (c == '\n')
serial_putc ('\r');
tmo = get_timer (0) + 1 * CFG_HZ;
tmo = get_timer (0) + 1 * CONFIG_SYS_HZ;
while (IO_SYSFLG1 & SYSFLG1_UTXFF)
if (get_timer (0) > tmo)
break;

2
cpu/arm720t/serial_netarm.c
View File

@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* wait until transmitter is ready for another character */
#define TXWAITRDY(registers) \
{ \
ulong tmo = get_timer(0) + 1 * CFG_HZ; \
ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \
while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \
if (get_timer(0) > tmo) \
break; \

12
cpu/arm720t/start.S
View File

@@ -166,8 +166,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -444,8 +444,8 @@ lock_loop:
add r8, sp, #S_PC
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -477,8 +477,8 @@ lock_loop:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

6
cpu/arm920t/at91rm9200/i2c.c
View File

@@ -120,7 +120,7 @@ int
i2c_read (unsigned char chip, unsigned int addr, int alen,
unsigned char *buffer, int len)
{
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/* we only allow one address byte */
if (alen > 1)
return 1;
@@ -139,7 +139,7 @@ int
i2c_write(unsigned char chip, unsigned int addr, int alen,
unsigned char *buffer, int len)
{
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
int i;
unsigned char *buf;
@@ -210,7 +210,7 @@ int i2c_set_bus_speed(unsigned int speed)
unsigned int i2c_get_bus_speed(void)
{
return CFG_I2C_SPEED;
return CONFIG_SYS_I2C_SPEED;
}
#endif /* CONFIG_HARD_I2C */

8
cpu/arm920t/at91rm9200/interrupts.c
View File

@@ -35,8 +35,8 @@
#include <asm/arch/hardware.h>
/*#include <asm/proc/ptrace.h>*/
/* the number of clocks per CFG_HZ */
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
/* the number of clocks per CONFIG_SYS_HZ */
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
/* macro to read the 16 bit timer */
#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
@@ -126,7 +126,7 @@ void udelay_masked (unsigned long usec)
ulong endtime;
signed long diff;
tmo = CFG_HZ_CLOCK / 1000;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;
@@ -155,7 +155,7 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

2
cpu/arm920t/at91rm9200/lowlevel_init.S
View File

@@ -79,7 +79,7 @@ lowlevel_init:
/* Get the CKGR Base Address */
ldr r1, =AT91C_BASE_CKGR
/* Main oscillator Enable register */
#ifdef CFG_USE_MAIN_OSCILLATOR
#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
#else
ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */

4
cpu/arm920t/at91rm9200/spi.c
View File

@@ -137,11 +137,11 @@ unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT));
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT){
if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}

4
cpu/arm920t/at91rm9200/usb.c
View File

@@ -23,7 +23,7 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# ifdef CONFIG_AT91RM9200
#include <asm/arch/hardware.h>
@@ -50,4 +50,4 @@ int usb_cpu_init_fail(void)
}
# endif /* CONFIG_AT91RM9200 */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

2
cpu/arm920t/cpu.c
View File

@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

2
cpu/arm920t/imx/interrupts.c
View File

@@ -112,7 +112,7 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

2
cpu/arm920t/interrupts.c
View File

@@ -42,7 +42,7 @@ void do_irq (struct pt_regs *pt_regs)
/* ASSUMED to be a timer interrupt */
/* Just clear it - count handled in */
/* integratorap.c */
*(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
#else
#error do_irq() not defined for this cpu type
#endif

8
cpu/arm920t/s3c24x0/i2c.c
View File

@@ -384,7 +384,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
xaddr[3] = addr & 0xFF;
}
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -397,7 +397,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
* hidden in the chip address.
*/
if (alen > 0)
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
if ((ret =
i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen,
@@ -423,7 +423,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
}
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -436,7 +436,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
* hidden in the chip address.
*/
if (alen > 0)
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
return (i2c_transfer
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,

2
cpu/arm920t/s3c24x0/interrupts.c
View File

@@ -179,7 +179,7 @@ ulong get_tbclk (void)
#elif defined(CONFIG_SBC2410X) || \
defined(CONFIG_SMDK2410) || \
defined(CONFIG_VCMA9)
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
#else
# error "tbclk not configured"
#endif

4
cpu/arm920t/s3c24x0/usb.c
View File

@@ -23,7 +23,7 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
#if defined(CONFIG_S3C2400)
@@ -69,4 +69,4 @@ int usb_cpu_init_fail (void)
}
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

12
cpu/arm920t/start.S
View File

@@ -202,8 +202,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -316,8 +316,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE)
sub r2, r2, #(CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -350,8 +350,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE)
sub r13, r13, #(CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

2
cpu/arm925t/cpu.c
View File

@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

18
cpu/arm925t/interrupts.c
View File

@@ -39,7 +39,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
static ulong timestamp;
static ulong lastdec;
@@ -50,9 +50,9 @@ int interrupt_init (void)
int32_t val;
/* Start the decrementer ticking down from 0xffffffff */
*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -86,10 +86,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -145,10 +145,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -178,6 +178,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

12
cpu/arm925t/start.S
View File

@@ -190,8 +190,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -295,8 +295,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -328,8 +328,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

8
cpu/arm926ejs/at91/spi.c
View File

@@ -48,7 +48,7 @@ void AT91F_SpiInit(void)
((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(0));
#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
/* Configure CS1 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
@@ -57,7 +57,7 @@ void AT91F_SpiInit(void)
AT91_BASE_SPI + AT91_SPI_CSR(1));
#endif
#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
/* Configure CS3 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
@@ -144,11 +144,11 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT) {
if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}

2
cpu/arm926ejs/at91/timer.c
View File

@@ -130,7 +130,7 @@ ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

4
cpu/arm926ejs/at91/usb.c
View File

@@ -23,7 +23,7 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
@@ -59,4 +59,4 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

2
cpu/arm926ejs/cpu.c
View File

@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

2
cpu/arm926ejs/davinci/i2c.c
View File

@@ -104,7 +104,7 @@ void i2c_init(int speed, int slaveadd)
}
psc = 2;
div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
REG(I2C_SCLH) = div - REG(I2C_SCLL);

48
cpu/arm926ejs/davinci/nand.c
View File

@@ -44,14 +44,14 @@
#include <common.h>
#include <asm/io.h>
#ifdef CFG_USE_NAND
#ifdef CONFIG_SYS_USE_NAND
#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
@@ -87,11 +87,11 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
#endif
}
#ifdef CFG_NAND_HW_ECC
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_NAND_HW_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
/* Linux-compatible ECC uses MTD defaults. */
/* These layouts are not compatible with Linux or RBL/UBL. */
#ifdef CFG_NAND_LARGEPAGE
#ifdef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout davinci_nand_ecclayout = {
.eccbytes = 12,
.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
@@ -103,7 +103,7 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
{.offset = 60, .length = 4}
}
};
#elif defined(CFG_NAND_SMALLPAGE)
#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
static struct nand_ecclayout davinci_nand_ecclayout = {
.eccbytes = 3,
.eccpos = {0, 1, 2},
@@ -113,9 +113,9 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
}
};
#else
#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
#endif
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
@@ -154,7 +154,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
{
u_int32_t tmp;
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
/*
* This is not how you should read ECCs on large page Davinci devices.
* The region parameter gets you ECCs for flash chips on different chip
@@ -191,11 +191,11 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
*ecc_code++ = tmp;
*ecc_code++ = tmp >> 8;
*ecc_code++ = tmp >> 16;
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
return(0);
}
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
{
u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
@@ -312,12 +312,12 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in
return(-1);
}
}
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
{
struct nand_chip *this = mtd->priv;
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
int block_count = 0, i, rc;
block_count = (this->ecc.size/512);
@@ -366,10 +366,10 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
return -1;
}
}
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
return(0);
}
#endif /* CFG_NAND_HW_ECC */
#endif /* CONFIG_SYS_NAND_HW_ECC */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
@@ -431,32 +431,32 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
nand->chip_delay = 0;
nand->select_chip = nand_davinci_select_chip;
#ifdef CFG_NAND_USE_FLASH_BBT
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
nand->options = NAND_USE_FLASH_BBT;
#endif
#ifdef CFG_NAND_HW_ECC
#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
nand->ecc.layout = &davinci_nand_ecclayout;
#ifdef CFG_NAND_LARGEPAGE
#ifdef CONFIG_SYS_NAND_LARGEPAGE
nand->ecc.size = 2048;
nand->ecc.bytes = 12;
#elif defined(CFG_NAND_SMALLPAGE)
#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
nand->ecc.size = 512;
nand->ecc.bytes = 3;
#else
#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
#endif
#else
nand->ecc.size = 512;
nand->ecc.bytes = 3;
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
nand->ecc.calculate = nand_davinci_calculate_ecc;
nand->ecc.correct = nand_davinci_correct_data;
nand->ecc.hwctl = nand_davinci_enable_hwecc;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif /* CFG_NAND_HW_ECC */
#endif /* CONFIG_SYS_NAND_HW_ECC */
/* Set address of hardware control function */
nand->cmd_ctrl = nand_davinci_hwcontrol;
@@ -472,4 +472,4 @@ int board_nand_init(struct nand_chip *nand)
#else
#error "U-Boot legacy NAND support not available for DaVinci chips"
#endif
#endif /* CFG_USE_NAND */
#endif /* CONFIG_SYS_USE_NAND */

8
cpu/arm926ejs/davinci/timer.c
View File

@@ -54,9 +54,9 @@ typedef volatile struct {
u_int32_t wdtcr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
static ulong timestamp;
@@ -117,7 +117,7 @@ void udelay(unsigned long usec)
ulong endtime;
signed long diff;
tmo = CFG_HZ_CLOCK / 1000;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= (1000 * TIM_CLK_DIV);
@@ -144,5 +144,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
return CFG_HZ;
return CONFIG_SYS_HZ;
}

18
cpu/arm926ejs/omap/timer.c
View File

@@ -41,7 +41,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
static ulong timestamp;
static ulong lastdec;
@@ -51,9 +51,9 @@ int timer_init (void)
int32_t val;
/* Start the decrementer ticking down from 0xffffffff */
*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -87,10 +87,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -140,10 +140,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -172,6 +172,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

12
cpu/arm926ejs/start.S
View File

@@ -165,8 +165,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -276,8 +276,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -310,8 +310,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

20
cpu/arm926ejs/versatile/timer.c
View File

@@ -41,7 +41,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
static ulong timestamp;
static ulong lastdec;
@@ -62,9 +62,9 @@ int timer_init (void)
ulong tmr_ctrl_val;
/* 1st disable the Timer */
tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~TIMER_ENABLE;
*(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/*
* The Timer Control Register has one Undefined/Shouldn't Use Bit
@@ -78,11 +78,11 @@ int timer_init (void)
* Tmr Siz : 16 Bit Counter
* Tmr in Wrapping Mode
*/
tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
*(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -116,10 +116,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -169,10 +169,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -201,6 +201,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

2
cpu/arm946es/cpu.c
View File

@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

6
cpu/arm946es/interrupts.c
View File

@@ -121,10 +121,10 @@ void udelay_masked (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ_CLOCK;
tmo = usec * CONFIG_SYS_HZ_CLOCK;
tmo /= (1000*1000);
}
@@ -151,7 +151,7 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

12
cpu/arm946es/start.S
View File

@@ -157,8 +157,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -264,8 +264,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -298,8 +298,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

2
cpu/arm_intcm/cpu.c
View File

@@ -43,7 +43,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

12
cpu/arm_intcm/start.S
View File

@@ -155,8 +155,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -240,8 +240,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -274,8 +274,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

24
cpu/at32ap/at32ap700x/clk.c
View File

@@ -38,10 +38,10 @@ void clk_init(void)
#ifdef CONFIG_PLL
/* Initialize the PLL */
sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
| SM_BF(PLLOPT, CFG_PLL0_OPT)
sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
| SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
| SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
| SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
| SM_BF(PLLOSC, 0)
| SM_BIT(PLLEN)));
@@ -51,14 +51,14 @@ void clk_init(void)
/* Set up clocks for the CPU and all peripheral buses */
cksel = 0;
if (CFG_CLKDIV_CPU)
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
if (CFG_CLKDIV_HSB)
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
if (CFG_CLKDIV_PBA)
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
if (CFG_CLKDIV_PBB)
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
if (CONFIG_SYS_CLKDIV_CPU)
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
if (CONFIG_SYS_CLKDIV_HSB)
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
if (CONFIG_SYS_CLKDIV_PBA)
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
if (CONFIG_SYS_CLKDIV_PBB)
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
sm_writel(PM_CKSEL, cksel);
#ifdef CONFIG_PLL

4
cpu/at32ap/at32ap700x/gpio.c
View File

@@ -33,8 +33,8 @@
*/
void gpio_enable_ebi(void)
{
#ifdef CFG_HSDRAMC
#ifndef CFG_SDRAM_16BIT
#ifdef CONFIG_SYS_HSDRAMC
#ifndef CONFIG_SYS_SDRAM_16BIT
gpio_select_periph_A(GPIO_PIN_PE0, 0);
gpio_select_periph_A(GPIO_PIN_PE1, 0);
gpio_select_periph_A(GPIO_PIN_PE2, 0);

8
cpu/at32ap/cache.c
View File

@@ -28,7 +28,7 @@ void dcache_clean_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
linesz = CFG_DCACHE_LINESZ;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
@@ -44,7 +44,7 @@ void dcache_invalidate_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
linesz = CFG_DCACHE_LINESZ;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
@@ -58,7 +58,7 @@ void dcache_flush_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
linesz = CFG_DCACHE_LINESZ;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);
@@ -74,7 +74,7 @@ void icache_invalidate_range(volatile void *start, size_t size)
{
unsigned long v, begin, end, linesz;
linesz = CFG_ICACHE_LINESZ;
linesz = CONFIG_SYS_ICACHE_LINESZ;
/* You asked for it, you got it */
begin = (unsigned long)start & ~(linesz - 1);

10
cpu/at32ap/cpu.c
View File

@@ -32,12 +32,12 @@
#include "hsmc3.h"
/* Sanity checks */
#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \
|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \
|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
#endif
#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
# error Invalid PLL multiplier and/or divider
#endif
@@ -47,7 +47,7 @@ int cpu_init(void)
{
extern void _evba(void);
gd->cpu_hz = CFG_OSC0_HZ;
gd->cpu_hz = CONFIG_SYS_OSC0_HZ;
/* TODO: Move somewhere else, but needs to be run before we
* increase the clock frequency. */

4
cpu/at32ap/hsdramc.c
View File

@@ -21,7 +21,7 @@
*/
#include <common.h>
#ifdef CFG_HSDRAMC
#ifdef CONFIG_SYS_HSDRAMC
#include <asm/io.h>
#include <asm/sdram.h>
@@ -117,4 +117,4 @@ unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
return sdram_size;
}
#endif /* CFG_HSDRAMC */
#endif /* CONFIG_SYS_HSDRAMC */

4
cpu/at32ap/interrupts.c
View File

@@ -82,7 +82,7 @@ void set_timer(unsigned long t)
unsigned long long ticks = t;
unsigned long lo, hi, hi_new;
ticks = (ticks * get_tbclk()) / CFG_HZ;
ticks = (ticks * get_tbclk()) / CONFIG_SYS_HZ;
hi = ticks >> 32;
lo = ticks & 0xffffffffUL;
@@ -137,7 +137,7 @@ void timer_init(void)
sysreg_write(COUNT, 0);
tmp = (u64)CFG_HZ << 32;
tmp = (u64)CONFIG_SYS_HZ << 32;
tmp += gd->cpu_hz / 2;
do_div(tmp, gd->cpu_hz);
tb_factor = (u32)tmp;

2
cpu/at32ap/start.S
View File

@@ -188,7 +188,7 @@ at32ap_low_level_init:
.align 2
.type sp_init,@object
sp_init:
.long CFG_INIT_SP_ADDR
.long CONFIG_SYS_INIT_SP_ADDR
got_init:
.long 3b - _GLOBAL_OFFSET_TABLE_

2
cpu/blackfin/interrupts.c
View File

@@ -48,7 +48,7 @@ ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

8
cpu/blackfin/start.S
View File

@@ -145,12 +145,12 @@ ENTRY(_start)
r6 = 0 (x);
p1 = r0;
p2.l = LO(CFG_MONITOR_BASE);
p2.h = HI(CFG_MONITOR_BASE);
p2.l = LO(CONFIG_SYS_MONITOR_BASE);
p2.h = HI(CONFIG_SYS_MONITOR_BASE);
p3 = 0x04;
p4.l = LO(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
p4.h = HI(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
p4.l = LO(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN);
p4.h = HI(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN);
.Lloop1:
r1 = [p1 ++ p3];
[p2 ++ p3] = r1;

4
cpu/blackfin/traps.c
View File

@@ -229,8 +229,8 @@ static void decode_address(char *buf, unsigned long address)
if (!address)
sprintf(buf, "<0x%p> /* Maybe null pointer? */", address);
else if (address >= CFG_MONITOR_BASE &&
address < CFG_MONITOR_BASE + CFG_MONITOR_LEN)
else if (address >= CONFIG_SYS_MONITOR_BASE &&
address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
sprintf(buf, "<0x%p> /* somewhere in u-boot */", address);
else
sprintf(buf, "<0x%p> /* unknown address */", address);

2
cpu/i386/interrupts.c
View File

@@ -509,7 +509,7 @@ int disable_interrupts(void)
}
#ifdef CFG_RESET_GENERIC
#ifdef CONFIG_SYS_RESET_GENERIC
void __attribute__ ((regparm(0))) generate_gpf(void);
asm(".globl generate_gpf\n"

12
cpu/i386/sc520.c
View File

@@ -113,7 +113,7 @@ void init_sc520(void)
write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
if (CFG_SC520_HIGH_SPEED) {
if (CONFIG_SYS_SC520_HIGH_SPEED) {
write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
@@ -145,7 +145,7 @@ unsigned long init_sc520_dram(void)
u32 dram_present=0;
u32 dram_ctrl;
#ifdef CFG_SDRAM_DRCTMCTL
#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
@@ -156,9 +156,9 @@ unsigned long init_sc520_dram(void)
#else
int val;
int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
int refresh_rate = CFG_SDRAM_REFRESH_RATE;
int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
/* set SDRAM speed here */
@@ -393,7 +393,7 @@ void pci_sc520_init(struct pci_controller *hose)
#endif
#ifdef CFG_TIMER_SC520
#ifdef CONFIG_SYS_TIMER_SC520
void reset_timer(void)

12
cpu/i386/sc520_asm.S
View File

@@ -460,21 +460,21 @@ emptybank:
incl %edi
loop cleanuplp
#if defined CFG_SDRAM_DRCTMCTL
#if defined CONFIG_SYS_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
movl $DRCTMCTL, %edi
movb $CFG_SDRAM_DRCTMCTL,%al
movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
movb (%edi), %al
#else
#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
/* set the CAS latency now since it is hard to do
* when we run from the RAM */
movl $DRCTMCTL, %edi /* DRAM timing register */
movb (%edi), %al
#ifdef CFG_SDRAM_CAS_LATENCY_2T
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
andb $0xef, %al
#endif
#ifdef CFG_SDRAM_CAS_LATENCY_3T
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
#endif
movb %al, (%edi)
@@ -540,7 +540,7 @@ bank0: movl (%edi), %eax
done:
movl %ebx, %eax
#if CFG_SDRAM_ECC_ENABLE
#if CONFIG_SYS_SDRAM_ECC_ENABLE
/* A nominal memory test: just a byte at each address line */
movl %eax, %ecx
shrl $0x1, %ecx

4
cpu/i386/start.S
View File

@@ -67,7 +67,7 @@ mem_init_ret:
* (we need atleast bss start+bss size+stack size) */
movl $_i386boot_bss_start, %ecx /* BSS start */
addl $_i386boot_bss_size, %ecx /* BSS size */
addl $CFG_STACK_SIZE, %ecx
addl $CONFIG_SYS_STACK_SIZE, %ecx
cmpl %ecx, %eax
jae mem_ok
@@ -88,7 +88,7 @@ mem_ok:
/* create a stack after the bss */
movl $_i386boot_bss_start, %eax
addl $_i386boot_bss_size, %eax
addl $CFG_STACK_SIZE, %eax
addl $CONFIG_SYS_STACK_SIZE, %eax
movl %eax, %esp
pushl $0

4
cpu/i386/timer.c
View File

@@ -72,9 +72,9 @@ int timer_init(void)
}
#ifdef CFG_TIMER_GENERIC
#ifdef CONFIG_SYS_TIMER_GENERIC
/* the unit for these is CFG_HZ */
/* the unit for these is CONFIG_SYS_HZ */
/* FixMe: implement these */
void reset_timer (void)

6
cpu/ixp/cpu.c
View File

@@ -81,7 +81,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
@@ -198,7 +198,7 @@ void pci_init(void)
void bootcount_store (ulong a)
{
volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
save_addr[0] = a;
save_addr[1] = BOOTCOUNT_MAGIC;
@@ -206,7 +206,7 @@ void bootcount_store (ulong a)
ulong bootcount_load (void)
{
volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
if (save_addr[1] != BOOTCOUNT_MAGIC)
return 0;

4
cpu/ixp/interrupts.c
View File

@@ -40,8 +40,8 @@
*/
#define FREQ 66666666
#define CLOCK_TICK_RATE (((FREQ / CFG_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CFG_HZ)
#define LATCH ((CLOCK_TICK_RATE + CFG_HZ/2) / CFG_HZ) /* For divider */
#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */
struct _irq_handler {
void *m_data;

6
cpu/ixp/npe/include/npe.h
View File

@@ -27,10 +27,10 @@
/*
* defines...
*/
#define CFG_NPE_NUMS 1
#define CONFIG_SYS_NPE_NUMS 1
#ifdef CONFIG_HAS_ETH1
#undef CFG_NPE_NUMS
#define CFG_NPE_NUMS 2
#undef CONFIG_SYS_NPE_NUMS
#define CONFIG_SYS_NPE_NUMS 2
#endif
#define NPE_NUM_PORTS 3

12
cpu/ixp/npe/npe.c
View File

@@ -51,7 +51,7 @@ static int npe_exists[NPE_NUM_PORTS];
static int npe_used[NPE_NUM_PORTS];
/* A little extra so we can align to cacheline. */
static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CFG_CACHELINE_SIZE - 1];
static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1];
static u8 *npe_alloc_end;
static u8 *npe_alloc_free;
@@ -60,7 +60,7 @@ static void *npe_alloc(int size)
static int count = 0;
void *p = NULL;
size = (size + (CFG_CACHELINE_SIZE-1)) & ~(CFG_CACHELINE_SIZE-1);
size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1);
count++;
if ((npe_alloc_free + size) < npe_alloc_end) {
@@ -399,7 +399,7 @@ static int npe_init(struct eth_device *dev, bd_t * bis)
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
/* initialize mbuf pool */
init_rx_mbufs(p_npe);
@@ -568,7 +568,7 @@ int npe_initialize(bd_t * bis)
int eth_num = 0;
struct npe *p_npe = NULL;
for (eth_num = 0; eth_num < CFG_NPE_NUMS; eth_num++) {
for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
@@ -673,8 +673,8 @@ int npe_initialize(bd_t * bis)
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
CFG_CACHELINE_SIZE - 1)
& ~(CFG_CACHELINE_SIZE - 1));
CONFIG_SYS_CACHELINE_SIZE - 1)
& ~(CONFIG_SYS_CACHELINE_SIZE - 1));
if (!npe_csr_load())
return 0;

12
cpu/ixp/serial.c
View File

@@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
unsigned int quot = 0;
int uart = CFG_IXP425_CONSOLE;
int uart = CONFIG_SYS_IXP425_CONSOLE;
if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
quot = SERIAL_CLOCK / gd->baudrate;
@@ -85,9 +85,9 @@ int serial_init (void)
void serial_putc (const char c)
{
/* wait for room in the tx FIFO on UART */
while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0);
while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0);
THR(CFG_IXP425_CONSOLE) = c;
THR(CONFIG_SYS_IXP425_CONSOLE) = c;
/* If \n, also do \r */
if (c == '\n')
@@ -101,7 +101,7 @@ void serial_putc (const char c)
*/
int serial_tstc (void)
{
return LSR(CFG_IXP425_CONSOLE) & LSR_DR;
return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
}
/*
@@ -111,9 +111,9 @@ int serial_tstc (void)
*/
int serial_getc (void)
{
while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR));
while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR));
return (char) RBR(CFG_IXP425_CONSOLE) & 0xff;
return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
void

22
cpu/ixp/start.S
View File

@@ -154,7 +154,7 @@ reset:
CPWAIT r0
/* set EXP CS0 to the optimum timing */
ldr r1, =CFG_EXP_CS0
ldr r1, =CONFIG_SYS_EXP_CS0
ldr r2, =IXP425_EXP_CS0
str r1, [r2]
@@ -165,7 +165,7 @@ reset:
orr r1, r1, #0x80000000
str r1, [r2]
#endif
mov r1, #CFG_SDR_CONFIG
mov r1, #CONFIG_SYS_SDR_CONFIG
ldr r2, =IXP425_SDR_CONFIG
str r1, [r2]
@@ -181,7 +181,7 @@ reset:
DELAY_FOR 0x4000, r0
/* set SDRAM internal refresh val */
ldr r1, =CFG_SDRAM_REFRESH_CNT
ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
str r1, [r3]
DELAY_FOR 0x4000, r0
@@ -199,7 +199,7 @@ reset:
bne 111b
/* set mode register in sdram */
mov r1, #CFG_SDR_MODE_CONFIG
mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
str r1, [r4]
DELAY_FOR 0x4000, r0
@@ -211,7 +211,7 @@ reset:
/* copy */
mov r0, #0
mov r4, r0
add r2, r0, #CFG_MONITOR_LEN
add r2, r0, #CONFIG_SYS_MONITOR_LEN
mov r1, #0x10000000
mov r5, r1
@@ -283,8 +283,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -345,8 +345,8 @@ _start_armboot: .word start_armboot
add r8, sp, #S_PC
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@@ -382,8 +382,8 @@ _start_armboot: .word start_armboot
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

2
cpu/ixp/timer.c
View File

@@ -44,7 +44,7 @@ void ixp425_udelay(unsigned long usec)
* This function has a max usec, but since it is called from udelay
* we should not have to worry... be happy
*/
unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;

8
cpu/leon2/interrupts.c
View File

@@ -98,8 +98,8 @@ static void leon2_ic_enable(unsigned int irq)
void handler_irq(int irq, struct pt_regs *regs)
{
if (irq_handlers[irq].handler) {
if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) ||
((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE)
if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
) {
printf("handler_irq: bad handler: %x, irq number %d\n",
(unsigned int)irq_handlers[irq].handler, irq);
@@ -163,8 +163,8 @@ void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler, (ulong) irq_handlers[irq].handler);
if (((unsigned int)handler > CFG_RAM_END) ||
((unsigned int)handler < CFG_RAM_BASE)
if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
((unsigned int)handler < CONFIG_SYS_RAM_BASE)
) {
printf("irq_install_handler: bad handler: %x, irq number %d\n",
(unsigned int)handler, irq);

50
cpu/leon2/prom.c
View File

@@ -45,14 +45,14 @@ extern struct linux_romvec *kernel_arg_promvec;
/* for __va */
extern int __prom_start;
#define PAGE_OFFSET 0xf0000000
#define phys_base CFG_SDRAM_BASE
#define phys_base CONFIG_SYS_SDRAM_BASE
#define PROM_OFFS 8192
#define PROM_SIZE_MASK (PROM_OFFS-1)
#define __va(x) ( \
(void *)( ((unsigned long)(x))-PROM_OFFS+ \
(CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
(CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
)
#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE))
#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE))
struct property {
char *name;
@@ -540,13 +540,13 @@ static struct leon_prom_info PROM_DATA spi = {
__va(&spi.totphys),
{
NULL,
(char *)CFG_SDRAM_BASE,
(char *)CONFIG_SYS_SDRAM_BASE,
0,
},
__va(&spi.avail),
{
NULL,
(char *)CFG_SDRAM_BASE,
(char *)CONFIG_SYS_SDRAM_BASE,
0,
},
NULL, /* prommap_p */
@@ -654,7 +654,7 @@ static void PROM_TEXT leon_reboot(char *bcommand)
/* get physical address */
struct leon_prom_info *pspi =
(void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
unsigned int *srmmu_ctx_table;
@@ -707,7 +707,7 @@ static void PROM_TEXT leon_reboot_physical(char *bcommand)
srmmu_set_mmureg(0);
/* Hardcoded start address */
reset = CFG_MONITOR_BASE;
reset = CONFIG_SYS_MONITOR_BASE;
/* flush data cache */
sparc_dcache_flush_all();
@@ -762,7 +762,7 @@ static int PROM_TEXT no_nextnode(int node)
{
/* get physical address */
struct leon_prom_info *pspi =
(void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -777,7 +777,7 @@ static int PROM_TEXT no_child(int node)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -792,7 +792,7 @@ static struct property PROM_TEXT *find_property(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -811,7 +811,7 @@ static int PROM_TEXT no_proplen(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -827,7 +827,7 @@ static int PROM_TEXT no_getprop(int node, char *name, char *value)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -850,7 +850,7 @@ static char PROM_TEXT *no_nextprop(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
struct property *prop;
/* convert into virtual address */
@@ -906,7 +906,7 @@ void leon_prom_init(struct leon_prom_info *pspi)
pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
/* Set Available main memory size */
pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE;
pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
pspi->avail.num_bytes = pspi->totphys.num_bytes;
#undef nodes
@@ -951,7 +951,7 @@ extern unsigned short bss_start, bss_end;
int prom_init(void)
{
struct leon_prom_info *pspi = (void *)
((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET);
((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
/* disable mmu */
srmmu_set_mmureg(0x00000000);
@@ -977,7 +977,7 @@ void prepare_bootargs(char *bootargs)
/* if no bootargs set, skip copying ==> default bootline */
if (bootargs && (*bootargs != '\0')) {
pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
CFG_PROM_OFFSET);
CONFIG_SYS_PROM_OFFSET);
src = bootargs;
dst = &pspi->arg[0];
left = 255; /* max len */
@@ -994,7 +994,7 @@ void srmmu_init_cpu(unsigned int entry)
{
sparc_srmmu_setup *psrmmu_tables = (void *)
((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
CFG_PROM_OFFSET);
CONFIG_SYS_PROM_OFFSET);
/* Make context 0 (kernel's context) point
* to our prepared memory mapping
@@ -1010,21 +1010,21 @@ void srmmu_init_cpu(unsigned int entry)
#define PTE 2
#define ACC_SU_ALL 0x1c
psrmmu_tables->pgd_table[0xf0] =
(CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
(CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf1] =
((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf2] =
((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf3] =
((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf4] =
((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf5] =
((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf6] =
((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf7] =
((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
/* convert rom vec pointer to virtual address */
kernel_arg_promvec = (struct linux_romvec *)

2
cpu/leon2/serial.c
View File

@@ -57,7 +57,7 @@ int serial_init(void)
regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2;
#endif
regs->UART_Scaler = CFG_LEON2_UART1_SCALER;
regs->UART_Scaler = CONFIG_SYS_LEON2_UART1_SCALER;
/* Let bit 11 be unchanged (debug bit for GRMON) */
tmp = READ_WORD(regs->UART_Control);

36
cpu/leon2/start.S
View File

@@ -68,7 +68,7 @@ ARGPUSH = (WINDOWSIZE + 4)
MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
/* Number of register windows */
#ifndef CFG_SPARC_NWINDOWS
#ifndef CONFIG_SYS_SPARC_NWINDOWS
#error Must define number of SPARC register windows, default is 8
#endif
@@ -280,16 +280,16 @@ leon2_init_ioport:
leon2_init_mctrl:
/* memory config register 1 */
set CFG_GRLIB_MEMCFG1, %g2
set CONFIG_SYS_GRLIB_MEMCFG1, %g2
ld [%g1], %g3 !
and %g3, 0x300, %g3
or %g2, %g3, %g2
st %g2, [%g1 + LEON2_MCFG1]
set CFG_GRLIB_MEMCFG2, %g2 ! Load memory config register 2
set CONFIG_SYS_GRLIB_MEMCFG2, %g2 ! Load memory config register 2
#if !( defined(TSIM) || !defined(BZIMAGE))
st %g2, [%g1 + LEON2_MCFG2] ! only for prom version, else done by "dumon -i"
#endif
set CFG_GRLIB_MEMCFG3, %g2 ! Init FT register
set CONFIG_SYS_GRLIB_MEMCFG3, %g2 ! Init FT register
st %g2, [%g1 + LEON2_ECTRL]
ld [%g1 + LEON2_ECTRL], %g2
srl %g2, 30, %g2
@@ -310,7 +310,7 @@ leon2_init_psr:
nop
leon2_init_stackp:
set CFG_INIT_SP_OFFSET, %fp
set CONFIG_SYS_INIT_SP_OFFSET, %fp
andn %fp, 0x0f, %fp
sub %fp, 64, %sp
@@ -327,7 +327,7 @@ cpu_init_unreloc:
reloc:
set TEXT_START,%g2
set DATA_END,%g3
set CFG_RELOC_MONITOR_BASE,%g4
set CONFIG_SYS_RELOC_MONITOR_BASE,%g4
reloc_loop:
ldd [%g2],%l0
ldd [%g2+8],%l2
@@ -373,10 +373,10 @@ fixup_got:
set __got_end,%g3
/*
* new got offset = (old GOT-PTR (read with ld) -
* CFG_RELOC_MONITOR_BASE(from define) ) +
* CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) +
* Destination Address (from define)
*/
set CFG_RELOC_MONITOR_BASE,%g2
set CONFIG_SYS_RELOC_MONITOR_BASE,%g2
set TEXT_START, %g1
add %g4,%g2,%g4
sub %g4,%g1,%g4
@@ -397,7 +397,7 @@ got_loop:
prom_relocate:
set __prom_start, %g2
set __prom_end, %g3
set CFG_PROM_OFFSET, %g4
set CONFIG_SYS_PROM_OFFSET, %g4
prom_relocate_loop:
ldd [%g2],%l0
@@ -413,7 +413,7 @@ prom_relocate_loop:
* the new trap table address
*/
set CFG_RELOC_MONITOR_BASE, %g2
set CONFIG_SYS_RELOC_MONITOR_BASE, %g2
wr %g0, %g2, %tbr
/* call relocate*/
@@ -421,14 +421,14 @@ prom_relocate_loop:
/* Call relocated init functions */
jump:
set cpu_init_f2,%o1
set CFG_RELOC_MONITOR_BASE,%o2
set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
clr %o0
set board_init_f,%o1
set CFG_RELOC_MONITOR_BASE,%o2
set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
@@ -454,7 +454,7 @@ _irq_entry:
WRITE_PAUSE
mov %l7, %o0 ! irq level
set handler_irq, %o1
set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2
set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2
add %o1, %o2, %o1
call %o1
add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
@@ -472,7 +472,7 @@ _window_overflow:
mov %wim, %l3 ! Calculate next WIM
mov %g1, %l7
srl %l3, 1, %g1
sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4
sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4
or %l4, %g1, %g1
save ! Get into window to be saved.
@@ -509,7 +509,7 @@ _window_underflow:
mov %wim, %l3 ! Calculate next WIM
sll %l3, 1, %l4
srl %l3, (CFG_SPARC_NWINDOWS-1), %l5
srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
or %l5, %l4, %l5
mov %l5, %wim
nop; nop; nop
@@ -578,7 +578,7 @@ trap_setup:
*/
srl %t_wim, 0x1, %g2 ! begin computation of new %wim
set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
sll %t_wim, %g3, %t_wim ! NWINDOWS-1
or %t_wim, %g2, %g2
@@ -612,7 +612,7 @@ ret_trap_entry:
mov 2, %g1
sll %g1, %t_psr, %g1
set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS
set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS
srl %g1, %g2, %g2
or %g1, %g2, %g1
@@ -622,7 +622,7 @@ ret_trap_entry:
sll %g2, 0x1, %g1
/* We have to grab a window before returning. */
set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
srl %g2, %g3, %g2
or %g1, %g2, %g1

20
cpu/leon3/cpu_init.c
View File

@@ -159,9 +159,9 @@ int init_memory_ctrl()
mctrl = (ambapp_dev_mctrl *) base;
/* config MCTRL memory controller */
mctrl->mcfg1 = CFG_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300);
mctrl->mcfg2 = CFG_GRLIB_MEMCFG2;
mctrl->mcfg3 = CFG_GRLIB_MEMCFG3;
mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300);
mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2;
mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3;
not_found_mctrl = 0;
}
@@ -171,9 +171,9 @@ int init_memory_ctrl()
mctrl = (ambapp_dev_mctrl *) base;
/* config MCTRL memory controller */
mctrl->mcfg1 = CFG_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300);
mctrl->mcfg2 = CFG_GRLIB_FT_MEMCFG2;
mctrl->mcfg3 = CFG_GRLIB_FT_MEMCFG3;
mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300);
mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2;
mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3;
not_found_mctrl = 0;
}
@@ -183,7 +183,7 @@ int init_memory_ctrl()
sdctrl = (ambapp_dev_sdctrl *) base;
/* config memory controller */
sdctrl->sdcfg = CFG_GRLIB_SDRAM;
sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM;
not_found_mctrl = 0;
}
@@ -192,8 +192,8 @@ int init_memory_ctrl()
ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1);
/* Config DDR2 memory controller */
ddr2spa->cfg1 = CFG_GRLIB_DDR2_CFG1;
ddr2spa->cfg3 = CFG_GRLIB_DDR2_CFG3;
ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1;
ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3;
not_found_mctrl = 0;
}
@@ -202,7 +202,7 @@ int init_memory_ctrl()
ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1);
/* Config DDR memory controller */
ddrspa->ctrl = CFG_GRLIB_DDR_CFG;
ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG;
not_found_mctrl = 0;
}

8
cpu/leon3/interrupts.c
View File

@@ -104,8 +104,8 @@ static void leon3_ic_enable(unsigned int irq)
void handler_irq(int irq, struct pt_regs *regs)
{
if (irq_handlers[irq].handler) {
if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) ||
((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE)
if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
) {
printf("handler_irq: bad handler: %x, irq number %d\n",
(unsigned int)irq_handlers[irq].handler, irq);
@@ -165,8 +165,8 @@ void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler, (ulong) irq_handlers[irq].handler);
if (((unsigned int)handler > CFG_RAM_END) ||
((unsigned int)handler < CFG_RAM_BASE)
if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
((unsigned int)handler < CONFIG_SYS_RAM_BASE)
) {
printf("irq_install_handler: bad handler: %x, irq number %d\n",
(unsigned int)handler, irq);

52
cpu/leon3/prom.c
View File

@@ -49,14 +49,14 @@ ambapp_dev_gptimer *gptimer;
/* for __va */
extern int __prom_start;
#define PAGE_OFFSET 0xf0000000
#define phys_base CFG_SDRAM_BASE
#define phys_base CONFIG_SYS_SDRAM_BASE
#define PROM_OFFS 8192
#define PROM_SIZE_MASK (PROM_OFFS-1)
#define __va(x) ( \
(void *)( ((unsigned long)(x))-PROM_OFFS+ \
(CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
(CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
)
#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE))
#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE))
struct property {
char *name;
@@ -545,13 +545,13 @@ static struct leon_prom_info PROM_DATA spi = {
__va(&spi.totphys),
{
NULL,
(char *)CFG_SDRAM_BASE,
(char *)CONFIG_SYS_SDRAM_BASE,
0,
},
__va(&spi.avail),
{
NULL,
(char *)CFG_SDRAM_BASE,
(char *)CONFIG_SYS_SDRAM_BASE,
0,
},
NULL, /* prommap_p */
@@ -659,7 +659,7 @@ static void PROM_TEXT leon_reboot(char *bcommand)
/* get physical address */
struct leon_prom_info *pspi =
(void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
unsigned int *srmmu_ctx_table;
@@ -712,7 +712,7 @@ static void PROM_TEXT leon_reboot_physical(char *bcommand)
srmmu_set_mmureg(0);
/* Hardcoded start address */
reset = CFG_MONITOR_BASE;
reset = CONFIG_SYS_MONITOR_BASE;
/* flush data cache */
sparc_dcache_flush_all();
@@ -742,7 +742,7 @@ static int PROM_TEXT leon_nbputchar(int c)
/* get physical address */
struct leon_prom_info *pspi =
(void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
uart = (ambapp_dev_apbuart *)
SPARC_BYPASS_READ(&pspi->reloc_funcs.leon3_apbuart);
@@ -778,7 +778,7 @@ static int PROM_TEXT no_nextnode(int node)
{
/* get physical address */
struct leon_prom_info *pspi =
(void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -793,7 +793,7 @@ static int PROM_TEXT no_child(int node)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -808,7 +808,7 @@ static struct property PROM_TEXT *find_property(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -827,7 +827,7 @@ static int PROM_TEXT no_proplen(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -843,7 +843,7 @@ static int PROM_TEXT no_getprop(int node, char *name, char *value)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
/* convert into virtual address */
pspi = (struct leon_prom_info *)
@@ -866,7 +866,7 @@ static char PROM_TEXT *no_nextprop(int node, char *name)
{
/* get physical address */
struct leon_prom_info *pspi = (struct leon_prom_info *)
(CFG_PROM_OFFSET + sizeof(srmmu_tables));
(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
struct property *prop;
/* convert into virtual address */
@@ -922,7 +922,7 @@ void leon_prom_init(struct leon_prom_info *pspi)
pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
/* Set Available main memory size */
pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE;
pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
pspi->avail.num_bytes = pspi->totphys.num_bytes;
/* Set the pointer to the Console UART in romvec */
@@ -982,7 +982,7 @@ extern unsigned short bss_start, bss_end;
int prom_init(void)
{
struct leon_prom_info *pspi = (void *)
((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET);
((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
/* disable mmu */
srmmu_set_mmureg(0x00000000);
@@ -1008,7 +1008,7 @@ void prepare_bootargs(char *bootargs)
/* if no bootargs set, skip copying ==> default bootline */
if (bootargs && (*bootargs != '\0')) {
pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
CFG_PROM_OFFSET);
CONFIG_SYS_PROM_OFFSET);
src = bootargs;
dst = &pspi->arg[0];
left = 255; /* max len */
@@ -1025,7 +1025,7 @@ void srmmu_init_cpu(unsigned int entry)
{
sparc_srmmu_setup *psrmmu_tables = (void *)
((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
CFG_PROM_OFFSET);
CONFIG_SYS_PROM_OFFSET);
/* Make context 0 (kernel's context) point
* to our prepared memory mapping
@@ -1041,21 +1041,21 @@ void srmmu_init_cpu(unsigned int entry)
#define PTE 2
#define ACC_SU_ALL 0x1c
psrmmu_tables->pgd_table[0xf0] =
(CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
(CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf1] =
((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf2] =
((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf3] =
((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf4] =
((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf5] =
((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf6] =
((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
psrmmu_tables->pgd_table[0xf7] =
((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
/* convert rom vec pointer to virtual address */
kernel_arg_promvec = (struct linux_romvec *)

2
cpu/leon3/serial.c
View File

@@ -58,7 +58,7 @@ int serial_init(void)
*
* Receiver & transmitter enable
*/
leon3_apbuart->scaler = CFG_GRLIB_APBUART_SCALER;
leon3_apbuart->scaler = CONFIG_SYS_GRLIB_APBUART_SCALER;
/* Let bit 11 be unchanged (debug bit for GRMON) */
tmp = READ_WORD(leon3_apbuart->ctrl);

34
cpu/leon3/start.S
View File

@@ -68,7 +68,7 @@ ARGPUSH = (WINDOWSIZE + 4)
MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
/* Number of register windows */
#ifndef CFG_SPARC_NWINDOWS
#ifndef CONFIG_SYS_SPARC_NWINDOWS
#error Must define number of SPARC register windows, default is 8
#endif
@@ -251,7 +251,7 @@ wininit:
mov %g3, %wim
stackp:
set CFG_INIT_SP_OFFSET, %fp
set CONFIG_SYS_INIT_SP_OFFSET, %fp
andn %fp, 0x0f, %fp
sub %fp, 64, %sp
@@ -268,7 +268,7 @@ cpu_init_unreloc:
reloc:
set TEXT_START,%g2
set DATA_END,%g3
set CFG_RELOC_MONITOR_BASE,%g4
set CONFIG_SYS_RELOC_MONITOR_BASE,%g4
reloc_loop:
ldd [%g2],%l0
ldd [%g2+8],%l2
@@ -314,10 +314,10 @@ fixup_got:
set __got_end,%g3
/*
* new got offset = (old GOT-PTR (read with ld) -
* CFG_RELOC_MONITOR_BASE(from define) ) +
* CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) +
* Destination Address (from define)
*/
set CFG_RELOC_MONITOR_BASE,%g2
set CONFIG_SYS_RELOC_MONITOR_BASE,%g2
set TEXT_START, %g1
add %g4,%g2,%g4
sub %g4,%g1,%g4
@@ -338,7 +338,7 @@ got_loop:
prom_relocate:
set __prom_start, %g2
set __prom_end, %g3
set CFG_PROM_OFFSET, %g4
set CONFIG_SYS_PROM_OFFSET, %g4
prom_relocate_loop:
ldd [%g2],%l0
@@ -354,7 +354,7 @@ prom_relocate_loop:
* the new trap table address
*/
set CFG_RELOC_MONITOR_BASE, %g2
set CONFIG_SYS_RELOC_MONITOR_BASE, %g2
wr %g0, %g2, %tbr
nop
nop
@@ -368,22 +368,22 @@ snoop_detect:
sethi %hi(0x00800000), %o0
lda [%g0] 2, %o1
and %o0, %o1, %o0
sethi %hi(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o1
st %o0, [%lo(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE)+%o1]
sethi %hi(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o1
st %o0, [%lo(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)+%o1]
/* call relocate*/
nop
/* Call relocated init functions */
jump:
set cpu_init_f2,%o1
set CFG_RELOC_MONITOR_BASE,%o2
set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
clr %o0
set board_init_f,%o1
set CFG_RELOC_MONITOR_BASE,%o2
set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
add %o1,%o2,%o1
sub %o1,%g1,%o1
call %o1
@@ -409,7 +409,7 @@ _irq_entry:
WRITE_PAUSE
mov %l7, %o0 ! irq level
set handler_irq, %o1
set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2
set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2
add %o1, %o2, %o1
call %o1
add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
@@ -427,7 +427,7 @@ _window_overflow:
mov %wim, %l3 ! Calculate next WIM
mov %g1, %l7
srl %l3, 1, %g1
sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4
sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4
or %l4, %g1, %g1
save ! Get into window to be saved.
@@ -464,7 +464,7 @@ _window_underflow:
mov %wim, %l3 ! Calculate next WIM
sll %l3, 1, %l4
srl %l3, (CFG_SPARC_NWINDOWS-1), %l5
srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
or %l5, %l4, %l5
mov %l5, %wim
nop; nop; nop
@@ -533,7 +533,7 @@ trap_setup:
*/
srl %t_wim, 0x1, %g2 ! begin computation of new %wim
set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
sll %t_wim, %g3, %t_wim ! NWINDOWS-1
or %t_wim, %g2, %g2
@@ -567,7 +567,7 @@ ret_trap_entry:
mov 2, %g1
sll %g1, %t_psr, %g1
set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS
set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS
srl %g1, %g2, %g2
or %g1, %g2, %g1
@@ -577,7 +577,7 @@ ret_trap_entry:
sll %g2, 0x1, %g1
/* We have to grab a window before returning. */
set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
srl %g2, %g3, %g2
or %g1, %g2, %g1

2
cpu/lh7a40x/cpu.c
View File

@@ -94,7 +94,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

10
cpu/lh7a40x/interrupts.c
View File

@@ -59,7 +59,7 @@ int interrupt_init (void)
/*
* 10ms period with 508.469kHz clock = 5084
*/
timer_load_val = CFG_HZ/100;
timer_load_val = CONFIG_SYS_HZ/100;
}
/* load value for 10 ms timeout */
@@ -98,12 +98,12 @@ void udelay (unsigned long usec)
/* normalize */
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CFG_HZ;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
}
else {
if (usec > 1) {
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
else
@@ -152,11 +152,11 @@ void udelay_masked (unsigned long usec)
/* normalize */
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CFG_HZ;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
if (usec > 1) {
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
} else {
tmo = 1;

12
cpu/lh7a40x/start.S
View File

@@ -172,8 +172,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -285,8 +285,8 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -318,8 +318,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

58
cpu/mcf5227x/cpu_init.c
View File

@@ -58,40 +58,40 @@ void cpu_init_f(void)
scm1->pacrg = 0;
scm1->pacri = 0;
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
fbcs->csar0 = CFG_CS0_BASE;
fbcs->cscr0 = CFG_CS0_CTRL;
fbcs->csmr0 = CFG_CS0_MASK;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK;
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK;
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK;
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK;
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
@@ -107,12 +107,12 @@ void cpu_init_f(void)
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
u32 oscillator = CFG_RTC_OSCILLATOR;
u32 oscillator = CONFIG_SYS_RTC_OSCILLATOR;
rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
#endif
return (0);
@@ -123,7 +123,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart &=
(GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);

8
cpu/mcf5227x/interrupts.c
View File

@@ -31,7 +31,7 @@
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
@@ -44,9 +44,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->imrh0 &= ~CFG_TMRINTR_MASK;
intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif

4
cpu/mcf5227x/speed.c
View File

@@ -99,14 +99,14 @@ int get_clocks(void)
/* serial mode */
} else {
/* Normal Mode */
vco = pfdr * CFG_INPUT_CLKSRC;
vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco;
}
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */

28
cpu/mcf5227x/start.S
View File

@@ -29,9 +29,9 @@
#endif
/* last three long word reserved for cache status */
#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
#define _START _start
#define _FAULT _fault
@@ -132,10 +132,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CFG_FLASH_BASE, %d0
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
@@ -156,7 +156,7 @@ _start:
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -187,7 +187,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -202,7 +202,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -212,9 +212,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -224,11 +224,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -240,7 +240,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -276,7 +276,7 @@ icache_enable:
move.l #0x01200000, %d0 /* Invalid cache */
movec %d0, %CACR
move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0
move.l #0x81600610, %d0 /* Enable cache */

2
cpu/mcf523x/cpu.c
View File

@@ -98,7 +98,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
wdp->mr = wdog_module;

72
cpu/mcf523x/cpu_init.c
View File

@@ -49,69 +49,69 @@ void cpu_init_f(void)
wdog->cr = 0;
#endif
scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
gpio->par_cs = 0;
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
fbcs->csar0 = CFG_CS0_BASE;
fbcs->cscr0 = CFG_CS0_CTRL;
fbcs->csmr0 = CFG_CS0_MASK;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS1;
fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS2;
fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK;
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS3;
fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK;
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS4;
fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS5;
fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL))
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS6;
fbcs->csar6 = CFG_CS6_BASE;
fbcs->cscr6 = CFG_CS6_CTRL;
fbcs->csmr6 = CFG_CS6_MASK;
fbcs->csar6 = CONFIG_SYS_CS6_BASE;
fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
#endif
#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL))
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS7;
fbcs->csar7 = CFG_CS7_BASE;
fbcs->cscr7 = CFG_CS7_CTRL;
fbcs->csmr7 = CFG_CS7_MASK;
fbcs->csar7 = CONFIG_SYS_CS7_BASE;
fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
#endif
#ifdef CONFIG_FSL_I2C
CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
icache_enable();
@@ -130,7 +130,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
break;

8
cpu/mcf523x/interrupts.c
View File

@@ -28,7 +28,7 @@
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrl0 |= 0x1;
@@ -40,10 +40,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrl0 &= ~INTC_IPRL_INT0;
intp->imrl0 &= ~CFG_TMRINTR_MASK;
intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif

2
cpu/mcf523x/speed.c
View File

@@ -42,7 +42,7 @@ int get_clocks(void)
while (!(pll->synsr & PLL_SYNSR_LOCK));
gd->bus_clk = CFG_CLK;
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C

40
cpu/mcf523x/start.S
View File

@@ -127,10 +127,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CFG_FLASH_BASE, %d0
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -143,14 +143,14 @@ _start:
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
move.l %d0, (%a1)
move.l %d0, (%a2)
/* set stackpointer to end of internal ram to get some stackspace for the
first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -181,7 +181,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
@@ -196,7 +196,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -206,9 +206,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -218,11 +218,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -234,7 +234,7 @@ clear_bss:
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
@@ -270,16 +270,16 @@ icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
nop
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80400100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -292,14 +292,14 @@ icache_disable:
movec %d0, %ACR0
movec %d0, %ACR1
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl icache_status
icache_status:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
move.l (%a1), %d0
rts
@@ -312,7 +312,7 @@ icache_invalid:
.globl dcache_enable
dcache_enable:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -320,14 +320,14 @@ dcache_enable:
/* No dcache, just a dummy function */
.globl dcache_disable
dcache_disable:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl dcache_status
dcache_status:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
move.l (%a1), %d0
rts

14
cpu/mcf52x2/cpu.c
View File

@@ -66,11 +66,11 @@ int checkcpu(void)
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
cpu_model, prn, strmhz(buf, CFG_CLK));
cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
pin, prn, strmhz(buf, CFG_CLK));
pin, prn, strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
@@ -174,7 +174,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdt->wdog_wrrr =
((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
wdt->wdog_wcr = 0; /* reset watchdog counter */
puts("WATCHDOG:enabled\n");
@@ -202,7 +202,7 @@ int checkcpu(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
strmhz(buf, CFG_CLK));
strmhz(buf, CONFIG_SYS_CLK));
return 0;
};
@@ -236,7 +236,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdt->wmr =
((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
wdt->wsr = 0x5555; /* reset watchdog counter */
wdt->wsr = 0xAAAA;
@@ -278,7 +278,7 @@ int checkcpu(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
strmhz(buf, CFG_CLK));
strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
@@ -300,7 +300,7 @@ int checkcpu(void)
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
strmhz(buf, CFG_CLK));
strmhz(buf, CONFIG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",

356
cpu/mcf52x2/cpu_init.c
View File

@@ -72,20 +72,20 @@ void cpu_init_f(void)
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
#ifdef CONFIG_FSL_I2C
CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#ifdef CFG_I2C2_OFFSET
CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
#endif
#endif
@@ -102,7 +102,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
break;
case 1:
@@ -138,7 +138,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
MCF_GPIO_PAR_UART_U0RXD);
@@ -169,59 +169,59 @@ void cpu_init_f(void)
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
sysctrl->sc_scr = CFG_SCR;
sysctrl->sc_spr = CFG_SPR;
sysctrl->sc_scr = CONFIG_SYS_SCR;
sysctrl->sc_spr = CONFIG_SYS_SPR;
/* Setup Ports: */
gpio->gpio_pacnt = CFG_PACNT;
gpio->gpio_paddr = CFG_PADDR;
gpio->gpio_padat = CFG_PADAT;
gpio->gpio_pbcnt = CFG_PBCNT;
gpio->gpio_pbddr = CFG_PBDDR;
gpio->gpio_pbdat = CFG_PBDAT;
gpio->gpio_pdcnt = CFG_PDCNT;
gpio->gpio_pacnt = CONFIG_SYS_PACNT;
gpio->gpio_paddr = CONFIG_SYS_PADDR;
gpio->gpio_padat = CONFIG_SYS_PADAT;
gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
/* Memory Controller: */
csctrl->cs_br0 = CFG_BR0_PRELIM;
csctrl->cs_or0 = CFG_OR0_PRELIM;
csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
csctrl->cs_br1 = CFG_BR1_PRELIM;
csctrl->cs_or1 = CFG_OR1_PRELIM;
#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
#endif
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
csctrl->cs_br2 = CFG_BR2_PRELIM;
csctrl->cs_or2 = CFG_OR2_PRELIM;
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
#endif
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
csctrl->cs_br3 = CFG_BR3_PRELIM;
csctrl->cs_or3 = CFG_OR3_PRELIM;
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
#endif
#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
csctrl->cs_br4 = CFG_BR4_PRELIM;
csctrl->cs_or4 = CFG_OR4_PRELIM;
#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
#endif
#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
csctrl->cs_br5 = CFG_BR5_PRELIM;
csctrl->cs_or5 = CFG_OR5_PRELIM;
#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
#endif
#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
csctrl->cs_br6 = CFG_BR6_PRELIM;
csctrl->cs_or6 = CFG_OR6_PRELIM;
#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
#endif
#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
csctrl->cs_br7 = CFG_BR7_PRELIM;
csctrl->cs_or7 = CFG_OR7_PRELIM;
#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
@@ -244,7 +244,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
@@ -282,57 +282,57 @@ void cpu_init_f(void)
/* Memory Controller: */
/* Flash */
csctrl_reg->ar0 = CFG_AR0_PRELIM;
csctrl_reg->cr0 = CFG_CR0_PRELIM;
csctrl_reg->mr0 = CFG_MR0_PRELIM;
csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM;
csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM;
csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM;
#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
csctrl_reg->ar1 = CFG_AR1_PRELIM;
csctrl_reg->cr1 = CFG_CR1_PRELIM;
csctrl_reg->mr1 = CFG_MR1_PRELIM;
#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM))
csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM;
csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM;
csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM;
#endif
#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
csctrl_reg->ar2 = CFG_AR2_PRELIM;
csctrl_reg->cr2 = CFG_CR2_PRELIM;
csctrl_reg->mr2 = CFG_MR2_PRELIM;
#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM))
csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM;
csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM;
csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM;
#endif
#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
csctrl_reg->ar3 = CFG_AR3_PRELIM;
csctrl_reg->cr3 = CFG_CR3_PRELIM;
csctrl_reg->mr3 = CFG_MR3_PRELIM;
#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM))
csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM;
csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM;
csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM;
#endif
#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
csctrl_reg->ar4 = CFG_AR4_PRELIM;
csctrl_reg->cr4 = CFG_CR4_PRELIM;
csctrl_reg->mr4 = CFG_MR4_PRELIM;
#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM))
csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM;
csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM;
csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM;
#endif
#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
csctrl_reg->ar5 = CFG_AR5_PRELIM;
csctrl_reg->cr5 = CFG_CR5_PRELIM;
csctrl_reg->mr5 = CFG_MR5_PRELIM;
#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM))
csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM;
csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM;
csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM;
#endif
#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
csctrl_reg->ar6 = CFG_AR6_PRELIM;
csctrl_reg->cr6 = CFG_CR6_PRELIM;
csctrl_reg->mr6 = CFG_MR6_PRELIM;
#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM))
csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM;
csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM;
csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM;
#endif
#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
csctrl_reg->ar7 = CFG_AR7_PRELIM;
csctrl_reg->cr7 = CFG_CR7_PRELIM;
csctrl_reg->mr7 = CFG_MR7_PRELIM;
#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM))
csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM;
csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM;
csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@@ -352,7 +352,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart |= UART0_ENABLE_MASK;
break;
@@ -384,155 +384,155 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
#ifdef CFG_PEPAR
MCFGPIO_PEPAR = CFG_PEPAR;
#ifdef CONFIG_SYS_PEPAR
MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
#endif
#ifdef CFG_PFPAR
MCFGPIO_PFPAR = CFG_PFPAR;
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
#ifdef CFG_PJPAR
MCFGPIO_PJPAR = CFG_PJPAR;
#ifdef CONFIG_SYS_PJPAR
MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
#endif
#ifdef CFG_PSDPAR
MCFGPIO_PSDPAR = CFG_PSDPAR;
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
#ifdef CFG_PASPAR
MCFGPIO_PASPAR = CFG_PASPAR;
#ifdef CONFIG_SYS_PASPAR
MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
#endif
#ifdef CFG_PEHLPAR
MCFGPIO_PEHLPAR = CFG_PEHLPAR;
#ifdef CONFIG_SYS_PEHLPAR
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
#endif
#ifdef CFG_PQSPAR
MCFGPIO_PQSPAR = CFG_PQSPAR;
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
#endif
#ifdef CFG_PTCPAR
MCFGPIO_PTCPAR = CFG_PTCPAR;
#ifdef CONFIG_SYS_PTCPAR
MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
#endif
#ifdef CFG_PTDPAR
MCFGPIO_PTDPAR = CFG_PTDPAR;
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
#ifdef CFG_PUAPAR
MCFGPIO_PUAPAR = CFG_PUAPAR;
#ifdef CONFIG_SYS_PUAPAR
MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#endif
#ifdef CFG_DDRUA
MCFGPIO_DDRUA = CFG_DDRUA;
#ifdef CONFIG_SYS_DDRUA
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
/* This is probably a bad place to setup chip selects, but everyone
else is doing it! */
#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \
defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS)
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF;
#if (CFG_CS0_WIDTH == 8)
#define CFG_CS0_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS0_WIDTH == 16)
#define CFG_CS0_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS0_WIDTH == 32)
#define CFG_CS0_PS MCFCSM_CSCR_PS_32
#if (CONFIG_SYS_CS0_WIDTH == 8)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS0_WIDTH == 16)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS0_WIDTH == 32)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
#error "CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
| CFG_CS0_PS | MCFCSM_CSCR_AA;
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS)
| CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA;
#if (CFG_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
#if (CONFIG_SYS_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \
defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF;
#if (CFG_CS1_WIDTH == 8)
#define CFG_CS1_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS1_WIDTH == 16)
#define CFG_CS1_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS1_WIDTH == 32)
#define CFG_CS1_PS MCFCSM_CSCR_PS_32
#if (CONFIG_SYS_CS1_WIDTH == 8)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS1_WIDTH == 16)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS1_WIDTH == 32)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
#error "CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
| CFG_CS1_PS | MCFCSM_CSCR_AA;
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS)
| CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA;
#if (CFG_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
#if (CONFIG_SYS_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \
defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF;
#if (CFG_CS2_WIDTH == 8)
#define CFG_CS2_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS2_WIDTH == 16)
#define CFG_CS2_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS2_WIDTH == 32)
#define CFG_CS2_PS MCFCSM_CSCR_PS_32
#if (CONFIG_SYS_CS2_WIDTH == 8)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS2_WIDTH == 16)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS2_WIDTH == 32)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
#error "CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2"
#endif
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
| CFG_CS2_PS | MCFCSM_CSCR_AA;
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS)
| CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA;
#if (CFG_CS2_RO != 0)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
#if (CONFIG_SYS_CS2_RO != 0)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 2 are not initialized/used"
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \
defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS)
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF;
#if (CFG_CS3_WIDTH == 8)
#define CFG_CS3_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS3_WIDTH == 16)
#define CFG_CS3_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS3_WIDTH == 32)
#define CFG_CS3_PS MCFCSM_CSCR_PS_32
#if (CONFIG_SYS_CS3_WIDTH == 8)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS3_WIDTH == 16)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS3_WIDTH == 32)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
#error "CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
| CFG_CS3_PS | MCFCSM_CSCR_AA;
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS)
| CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA;
#if (CFG_CS3_RO != 0)
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
#if (CONFIG_SYS_CS3_RO != 0)
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
@@ -556,7 +556,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
MCFGPIO_PUAPAR &= 0xFc;
MCFGPIO_PUAPAR |= 0x03;
@@ -589,12 +589,12 @@ void cpu_init_f(void)
* which is their primary function.
* ~Jeremy
*/
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
@@ -636,13 +636,13 @@ void cpu_init_f(void)
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
/* enable instruction cache now */
icache_enable();
@@ -659,7 +659,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
break;
case 1:

14
cpu/mcf52x2/interrupts.c
View File

@@ -51,10 +51,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE);
volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
intp->int_icr1 |= CFG_TMRINTR_PRI;
intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
@@ -62,7 +62,7 @@ void dtimer_intr_setup(void)
#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrl0 |= 0x1;
@@ -74,11 +74,11 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrl0 &= 0xFFFFFFFE;
intp->imrl0 &= ~CFG_TMRINTR_MASK;
intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -95,7 +95,7 @@ int interrupt_init(void)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */

12
cpu/mcf52x2/speed.c
View File

@@ -39,11 +39,11 @@ int get_clocks (void)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#ifndef CFG_PLL_BYPASS
#ifndef CONFIG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
#ifdef CFG_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@ -51,7 +51,7 @@ int get_clocks (void)
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
pllcr = CFG_PLLCR;
pllcr = CONFIG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -60,7 +60,7 @@ int get_clocks (void)
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
#endif /* #ifndef CFG_PLL_BYPASS */
#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -76,7 +76,7 @@ int get_clocks (void)
;
#endif
gd->cpu_clk = CFG_CLK;
gd->cpu_clk = CONFIG_SYS_CLK;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
@@ -85,7 +85,7 @@ int get_clocks (void)
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#ifdef CFG_I2C2_OFFSET
#ifdef CONFIG_SYS_I2C2_OFFSET
gd->i2c2_clk = gd->bus_clk;
#endif
#endif

76
cpu/mcf52x2/start.S
View File

@@ -56,7 +56,7 @@
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -103,9 +103,9 @@ _vectors:
.text
#if defined(CFG_INT_FLASH_BASE) && \
#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@@ -120,44 +120,44 @@ _start:
move.w #0x2700,%sr
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
#ifdef CFG_MBAR2
move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
#ifdef CONFIG_SYS_MBAR2
move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */
movec %d0, #0xc0e /* Set MBAR2 */
#endif
move.l #(CFG_INIT_RAM_ADDR + 1), %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
move.l #(CFG_INIT_RAM_ADDR), %a2
move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
jmp CFG_INIT_RAM_ADDR
jmp CONFIG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@@ -165,9 +165,9 @@ _flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
#endif
#endif
@@ -175,22 +175,22 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
move.l #CFG_INT_FLASH_BASE, %d0
#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
#else
move.l #CFG_FLASH_BASE, %d0
move.l #CONFIG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* Initialize IPSBAR */
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@@ -204,7 +204,7 @@ _after_flashbar_copy:
#endif
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -235,7 +235,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
@@ -249,7 +249,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -259,9 +259,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -271,11 +271,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -290,27 +290,27 @@ clear_bss:
/* quick and dirty */
move.l %a0,%d1
add.l #(icache_state - CFG_MONITOR_BASE),%d1
add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
move.l %a0,%a1
add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
#endif
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
defined(CFG_HALT_BEFOR_RAM_JUMP)
#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
halt
#endif
jsr (%a1)
@@ -344,14 +344,14 @@ _int_handler:
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts

2
cpu/mcf532x/cpu.c
View File

@@ -117,7 +117,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
wdp->mr = (wdog_module / 8192);
#else

50
cpu/mcf532x/cpu_init.c
View File

@@ -63,46 +63,46 @@ void cpu_init_f(void)
/* Port configuration */
gpio->par_cs = 0;
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
fbcs->csar0 = CFG_CS0_BASE;
fbcs->cscr0 = CFG_CS0_CTRL;
fbcs->csmr0 = CFG_CS0_MASK;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1;
fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2;
fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK;
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3;
fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK;
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
@@ -125,7 +125,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
break;

8
cpu/mcf532x/interrupts.c
View File

@@ -28,7 +28,7 @@
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
@@ -41,9 +41,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->imrh0 &= ~CFG_TMRINTR_MASK;
intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif

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