Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
- fix SRAM and SDRAM memory sizing - add status LED support - add MAC address for second (SCC1) ethernet port Update default environment for TQM8260 board
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wdenk
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@ -2,6 +2,13 @@
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Changes since U-Boot 0.2.2:
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======================================================================
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* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
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- fix SRAM and SDRAM memory sizing
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- add status LED support
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- add MAC address for second (SCC1) ethernet port
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* Update default environment for TQM8260 board
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* Patch by Rick Bronson, 16 Mar 2003:
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- Add NAND flash support for reading, writing, and erasing NAND
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flash (certain forms of which are called SmartMedia).
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@ -28,6 +28,9 @@
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#include <net.h> /* for eth_init() */
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#include <rtc.h>
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#include "sixnet.h"
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#ifdef CONFIG_SHOW_BOOT_PROGRESS
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# include <status_led.h>
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#endif
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#define ORMASK(size) ((-size) & OR_AM_MSK)
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@ -35,6 +38,22 @@ static long ram_size(ulong *, long);
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_SHOW_BOOT_PROGRESS
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void show_boot_progress (int status)
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{
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#if defined(CONFIG_STATUS_LED)
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# if defined(STATUS_LED_BOOT)
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if (status == 15) {
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/* ready to transfer to kernel, make sure LED is proper state */
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status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
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}
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# endif /* STATUS_LED_BOOT */
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#endif /* CONFIG_STATUS_LED */
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}
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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* returns 0 if recognized, -1 if unknown
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@ -235,6 +254,9 @@ int misc_init_r (void)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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char* s;
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char* e;
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int reg;
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bd_t *bd = gd->bd;
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memctl->memc_or2 = NVRAM_OR_PRELIM;
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@ -283,18 +305,19 @@ int misc_init_r (void)
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immap->im_sit.sit_rtc = tim;
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}
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#if 0
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/* The code below is no longer valid since the prototype of
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* eth_init() and eth_halt() have been changed to support
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* multi-ethernet feature in U-Boot; the eth_initialize()
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* routine should be called before any access to the ethernet
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* callbacks.
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/* set up ethernet address for SCC ethernet. If eth1addr
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* is present it gets a unique address, otherwise it
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* shares the FEC address.
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*/
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s = getenv("eth1addr");
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if (s == NULL)
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s = getenv("ethaddr");
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for (reg=0; reg<6; ++reg) {
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bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
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if (s)
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s = (*e) ? e+1 : e;
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}
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/* FIXME - for now init ethernet to force PHY special mode */
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eth_init(bd);
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eth_halt();
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#endif
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return (0);
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}
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@ -307,7 +330,7 @@ int misc_init_r (void)
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*
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* The memory size MUST be a power of 2 for this to work.
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*
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* The only memory modified is 4 bytes at offset 0. This is important
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* The only memory modified is 8 bytes at offset 0. This is important
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* since for the SRAM this location is reserved for autosizing, so if
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* it is modified and the board is reset before ram_size() completes
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* no damage is done. Normally even the memory at 0 is preserved. The
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@ -319,28 +342,27 @@ static long ram_size(ulong *base, long maxsize)
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{
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volatile long *test_addr;
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volatile long *base_addr = base;
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volatile long *flash = (volatile long*)CFG_FLASH_BASE;
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ulong ofs; /* byte offset from base_addr */
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ulong save; /* to make test non-destructive */
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ulong junk;
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ulong save2; /* to make test non-destructive */
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long ramsize = -1; /* size not determined yet */
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save = *base_addr; /* save value at 0 so can restore */
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save2 = *(base_addr+1); /* save value at 4 so can restore */
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/* is any SRAM present? */
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*base_addr = 0x5555aaaa;
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/* use flash read to modify data bus, since with no SRAM present
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* the data bus may retain the value if our code is running
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* completely in the cache.
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/* It is important to drive the data bus with different data so
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* it doesn't remember the value and look like RAM that isn't there.
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*/
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junk = *flash;
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*(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
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if (*base_addr != 0x5555aaaa)
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ramsize = 0; /* no RAM present, or defective */
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else {
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*base_addr = 0xaaaa5555;
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junk = *flash; /* use flash read to modify data bus */
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*(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
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if (*base_addr != 0xaaaa5555)
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ramsize = 0; /* no RAM present, or defective */
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}
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@ -355,6 +377,7 @@ static long ram_size(ulong *base, long maxsize)
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}
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*base_addr = save; /* restore value at 0 */
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*(base_addr+1) = save2; /* restore value at 4 */
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return (ramsize);
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}
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@ -426,18 +449,21 @@ const uint sdram_table[] =
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MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
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/* MAMR values work in either mamr or mbmr */
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/* 8 column SDRAM */
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#define SDRAM_MAMR_8COL /* refresh at 50MHz */ \
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#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
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((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
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| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
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| MAMR_DSA_1_CYCL /* 1 cycle disable */ \
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| MAMR_G0CLA_A11 /* GPL0 A11[MPC] */ \
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| MAMR_RLFA_1X /* Read loop 1 time */ \
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| MAMR_WLFA_1X /* Write loop 1 time */ \
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| MAMR_TLFA_4X) /* Timer loop 4 times */
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/* 8 column SDRAM */
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#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
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| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
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| MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
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/* 9 column SDRAM */
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#define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
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#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
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| MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
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| MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
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/* base address 0, 32-bit port, SDRAM UPM, valid */
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#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
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@ -68,7 +68,10 @@ typedef struct bd_info {
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#if defined(CONFIG_HYMOD)
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hymod_conf_t bi_hymod_conf; /* hymod configuration information */
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#endif
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#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62) || defined(CONFIG_SVM_SC8xx)
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#if defined(CONFIG_EVB64260) || \
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defined(CONFIG_PN62) || \
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defined(CONFIG_SXNI855T) || \
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defined(CONFIG_SVM_SC8xx)
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/* second onboard ethernet port */
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unsigned char bi_enet1addr[6];
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#endif
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@ -81,6 +81,32 @@
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for status LED
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*/
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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# define STATUS_LED_PAR im_ioport.iop_papar
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# define STATUS_LED_DIR im_ioport.iop_padir
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# define STATUS_LED_ODR im_ioport.iop_paodr
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# define STATUS_LED_DAT im_ioport.iop_padat
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# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
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# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
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# define STATUS_LED_STATE STATUS_LED_BLINKING
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# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
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# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
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#ifdef DEV /* development (debug) settings */
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#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
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#else /* production settings */
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#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
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#endif
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
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@ -69,11 +69,25 @@
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):$(netdev):off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm $(kernel_addr)\0" \
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"flash_self=run ramargs addip;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/TQM8260/uImage\0" \
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"kernel_addr=40040000\0" \
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"ramdisk_addr=40100000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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