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Merge branch 'master' of git://git.denx.de/u-boot-sunxi

Browse Source 
- H6 Beelink GS1 board (Clément)
- Olimex A64-Teres-I board (Jonas)
- sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej)
- Change include order (Jagan)
- EPHY clock changes (Jagan)
- EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
This commit is contained in:
Tom Rini 2019-05-08 16:21:43 -04:00
commit 504bf790da
20 changed files with 798 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/Makefile
View File

@ -480,6 +480,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb
@ -494,7 +495,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb \
sun50i-a64-pinebook.dtb \
sun50i-a64-sopine-baseboard.dtb
sun50i-a64-sopine-baseboard.dtb \
sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \

41
arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi Normal file
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@ -0,0 +1,41 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Vasily Khoruzhick <anarsoul@gmail.com>
*
*/
#include "sunxi-u-boot.dtsi"
/ {
vdd_bl: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "bl-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
enable-active-high;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 0>;
brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
default-brightness-level = <2>;
enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
power-supply = <&vdd_bl>;
};
};
/* The ANX6345 eDP-bridge is on i2c */
&i2c0 {
anx6345: edp-bridge@38 {
compatible = "analogix,anx6345";
reg = <0x38>;
reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
status = "okay";
};
};
&pwm {
status = "okay";
};

270
arch/arm/dts/sun50i-a64-teres-i.dts Normal file
View File

@ -0,0 +1,270 @@
/*
* Copyright (C) Harald Geyer <harald@ccbib.org>
* based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Olimex A64 Teres-I";
compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
framebuffer-lcd {
eDP25-supply = <&reg_dldo2>;
eDP12-supply = <&reg_dldo3>;
};
};
gpio-keys {
compatible = "gpio-keys";
lid-switch {
label = "Lid Switch";
gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
capslock {
label = "teres-i:green:capslock";
gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
};
numlock {
label = "teres-i:green:numlock";
gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
};
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&ehci1 {
status = "okay";
};
/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
* driver for this chip at the moment, the bootloader initializes it.
* However it can be accessed with the i2c-dev driver from user space.
*/
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_aldo2>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
rtl8723bs: wifi@1 {
reg = <1>;
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
interrupt-names = "host-wake";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_rsb {
status = "okay";
axp803: pmic@3a3 {
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
#include "axp803.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc-pe";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pll-avcc";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1040000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-cpux";
};
/* DCDC3 is polyphased with DCDC2 */
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-ddr3";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-hdmi";
};
&reg_dldo2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pd";
};
&reg_dldo3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vdd-edp";
};
&reg_dldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-io";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "cpvdd";
};
&reg_eldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dvdd-csi";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-1v2-hsic";
};
/*
* The A64 chip cannot work without this regulator off, although
* it seems to be only driving the AR100 core.
* Maybe we don't still know well about CPUs domain.
*/
&reg_fldo2 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

184
arch/arm/dts/sun50i-h6-beelink-gs1.dts Normal file
View File

@ -0,0 +1,184 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2019 Clément Péron <peron.clem@gmail.com>
*/
/dts-v1/;
#include "sun50i-h6.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Beelink GS1";
compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
power {
label = "beelink:white:power";
gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
default-state = "on";
};
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC jack */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_cldo1>;
vqmmc-supply = <&reg_bldo2>;
non-removable;
cap-mmc-hw-reset;
bus-width = <8>;
status = "okay";
};
&r_i2c {
status = "okay";
axp805: pmic@36 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
vina-supply = <&reg_vcc5v>;
vinb-supply = <&reg_vcc5v>;
vinc-supply = <&reg_vcc5v>;
vind-supply = <&reg_vcc5v>;
vine-supply = <&reg_vcc5v>;
aldoin-supply = <&reg_vcc5v>;
bldoin-supply = <&reg_vcc5v>;
cldoin-supply = <&reg_vcc5v>;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ac200";
regulator-enable-ramp-delay = <100000>;
};
reg_aldo3: aldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc25-dram";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-bias-pll";
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-efuse-pcie-hdmi-io";
};
reg_bldo3: bldo3 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dcxoio";
};
bldo4 {
/* unused */
};
reg_cldo1: cldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
reg_cldo2: cldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-1";
};
reg_cldo3: cldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-2";
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <960000>;
regulator-name = "vdd-sys";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
sw {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

12
board/sunxi/MAINTAINERS
View File

@ -166,6 +166,12 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/bananapi_m64_defconfig
BEELINK GS1
M: Clément Péron <peron.clem@gmail.com>
S: Maintained
F: configs/beelink_gs1_defconfig
F: arch/arm/dts/sun50i-h6-beelink-gs1.dts
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@bootlin.com>
S: Maintained
@ -352,6 +358,12 @@ S: Maintained
F: configs/A20-Olimex-SOM204-EVB_defconfig
F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
OLIMEX TERES-I BOARD
M: Jonas Smedegaard <dr@jones.dk>
M: Icenowy Zheng <icenowy@aosc.io>
S: Maintained
F: configs/teres_i_defconfig
ORANGEPI LITE2 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

2
configs/Cubietruck_plus_defconfig
View File

@ -21,6 +21,8 @@ CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_AXP_FLDO1_VOLT=1200

4
configs/Sinovoip_BPI_M3_defconfig
View File

@ -22,8 +22,10 @@ CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3"
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO3_VOLT=3300
CONFIG_AXP_SW_ON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

15
configs/beelink_gs1_defconfig Normal file
View File

@ -0,0 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_PSCI_RESET is not set
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1"
CONFIG_LED=y
CONFIG_LED_GPIO=y

22
configs/teres_i_defconfig Normal file
View File

@ -0,0 +1,22 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i"
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
# CONFIG_USB_GADGET is not set
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

85
drivers/clk/clk-uclass.c
View File

@ -54,13 +54,51 @@ static int clk_of_xlate_default(struct clk *clk,
return 0;
}
static int clk_get_by_index_tail(int ret, ofnode node,
struct ofnode_phandle_args *args,
const char *list_name, int index,
struct clk *clk)
{
struct udevice *dev_clk;
const struct clk_ops *ops;
assert(clk);
clk->dev = NULL;
if (ret)
goto err;
ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
return ret;
}
clk->dev = dev_clk;
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
ret = ops->of_xlate(clk, args);
else
ret = clk_of_xlate_default(clk, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
}
return clk_request(dev_clk, clk);
err:
debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
__func__, ofnode_get_name(node), list_name, index, ret);
return ret;
}
static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
int index, struct clk *clk)
{
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_clk;
const struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
@ -75,32 +113,33 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
return ret;
}
clk->dev = dev_clk;
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
ret = ops->of_xlate(clk, &args);
else
ret = clk_of_xlate_default(clk, &args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
}
return clk_request(dev_clk, clk);
return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
index > 0, clk);
}
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
return clk_get_by_indexed_prop(dev, "clocks", index, clk);
struct ofnode_phandle_args args;
int ret;
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
index, &args);
return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
index > 0, clk);
}
int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
{
struct ofnode_phandle_args args;
int ret;
ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
index > 0, &args);
return clk_get_by_index_tail(ret, node, &args, "clocks",
index > 0, clk);
}
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)

2
drivers/clk/sifive/fu540-prci.c
View File

@ -28,10 +28,10 @@
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
*/
#include <common.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <clk.h>
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>

72
drivers/net/sun8i_emac.c
View File

@ -138,7 +138,9 @@ struct emac_eth_dev {
struct phy_device *phydev;
struct mii_dev *bus;
struct clk tx_clk;
struct clk ephy_clk;
struct reset_ctl tx_rst;
struct reset_ctl ephy_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
@ -653,7 +655,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int ret;
ret = clk_enable(&priv->tx_clk);
@ -670,16 +671,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
}
}
if (priv->variant == H3_EMAC) {
/* Only H3/H5 have clock controls for internal EPHY */
if (priv->use_internal_phy) {
/* Set clock gating for ephy */
setbits_le32(&ccm->bus_gate4,
BIT(AHB_GATE_OFFSET_EPHY));
/* Only H3/H5 have clock controls for internal EPHY */
if (clk_valid(&priv->ephy_clk)) {
ret = clk_enable(&priv->ephy_clk);
if (ret) {
dev_err(dev, "failed to enable EPHY TX clock\n");
return ret;
}
}
/* Deassert EPHY */
setbits_le32(&ccm->ahb_reset2_cfg,
BIT(AHB_RESET_OFFSET_EPHY));
if (reset_valid(&priv->ephy_rst)) {
ret = reset_deassert(&priv->ephy_rst);
if (ret) {
dev_err(dev, "failed to deassert EPHY TX clock\n");
return ret;
}
}
@ -839,6 +844,44 @@ static const struct eth_ops sun8i_emac_eth_ops = {
.stop = sun8i_emac_eth_stop,
};
static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
{
int node, ret;
/* look for mdio-mux node for internal PHY node */
node = fdt_path_offset(gd->fdt_blob,
"/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
if (node < 0) {
debug("failed to get mdio-mux with internal PHY\n");
return node;
}
ret = fdt_node_check_compatible(gd->fdt_blob, node,
"allwinner,sun8i-h3-mdio-internal");
if (ret < 0) {
debug("failed to find mdio-internal node\n");
return ret;
}
ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0,
&priv->ephy_clk);
if (ret) {
dev_err(dev, "failed to get EPHY TX clock\n");
return ret;
}
ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0,
&priv->ephy_rst);
if (ret) {
dev_err(dev, "failed to get EPHY TX reset\n");
return ret;
}
priv->use_internal_phy = true;
return 0;
}
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
@ -920,12 +963,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
}
if (priv->variant == H3_EMAC) {
int parent = fdt_parent_offset(gd->fdt_blob, offset);
if (parent >= 0 &&
!fdt_node_check_compatible(gd->fdt_blob, parent,
"allwinner,sun8i-h3-mdio-internal"))
priv->use_internal_phy = true;
ret = sun8i_get_ephy_nodes(priv);
if (ret)
return ret;
}
priv->interface = pdata->phy_interface;

53
drivers/reset/reset-uclass.c
View File

@ -29,41 +29,34 @@ static int reset_of_xlate_default(struct reset_ctl *reset_ctl,
return 0;
}
int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl)
static int reset_get_by_index_tail(int ret, ofnode node,
struct ofnode_phandle_args *args,
const char *list_name, int index,
struct reset_ctl *reset_ctl)
{
struct ofnode_phandle_args args;
int ret;
struct udevice *dev_reset;
struct reset_ops *ops;
debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
reset_ctl);
assert(reset_ctl);
reset_ctl->dev = NULL;
ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
index, &args);
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
__func__, ret);
if (ret)
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_RESET, args.node,
ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node,
&dev_reset);
if (ret) {
debug("%s: uclass_get_device_by_ofnode() failed: %d\n",
__func__, ret);
debug("%s %d\n", ofnode_get_name(args.node), args.args[0]);
debug("%s %d\n", ofnode_get_name(args->node), args->args[0]);
return ret;
}
ops = reset_dev_ops(dev_reset);
reset_ctl->dev = dev_reset;
if (ops->of_xlate)
ret = ops->of_xlate(reset_ctl, &args);
ret = ops->of_xlate(reset_ctl, args);
else
ret = reset_of_xlate_default(reset_ctl, &args);
ret = reset_of_xlate_default(reset_ctl, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
@ -78,6 +71,32 @@ int reset_get_by_index(struct udevice *dev, int index,
return 0;
}
int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl)
{
struct ofnode_phandle_args args;
int ret;
ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
index, &args);
return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets",
index > 0, reset_ctl);
}
int reset_get_by_index_nodev(ofnode node, int index,
struct reset_ctl *reset_ctl)
{
struct ofnode_phandle_args args;
int ret;
ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
index > 0, &args);
return reset_get_by_index_tail(ret, node, &args, "resets",
index > 0, reset_ctl);
}
int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
{
int i, ret, err, count;

2
drivers/serial/serial_sifive.c
View File

@ -3,8 +3,8 @@
* Copyright (C) 2018 Anup Patel <anup@brainfault.org>
*/
#include <clk.h>
#include <common.h>
#include <clk.h>
#include <debug_uart.h>
#include <dm.h>
#include <errno.h>

2
drivers/spi/atcspi200_spi.c
View File

@ -6,8 +6,8 @@
* Author: Rick Chen (rick@andestech.com)
*/
#include <clk.h>
#include <common.h>
#include <clk.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>

15
include/clk.h
View File

@ -8,6 +8,7 @@
#ifndef _CLK_H_
#define _CLK_H_
#include <dm/ofnode.h>
#include <linux/errno.h>
#include <linux/types.h>
@ -100,6 +101,20 @@ int clk_get_by_index_platdata(struct udevice *dev, int index,
*/
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
/**
* clock_get_by_index_nodev - Get/request a clock by integer index
* without a device.
*
* This is a version of clk_get_by_index() that does not use a device.
*
* @node: The client ofnode.
* @index: The index of the clock to request, within the client's list of
* clocks.
* @clock A pointer to a clock struct to initialize.
* @return 0 if OK, or a negative error code.
*/
int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk);
/**
* clock_get_bulk - Get/request all clocks of a device.
*

16
include/configs/sunxi-common.h
View File

@ -390,6 +390,18 @@ extern int soft_i2c_gpio_scl;
#define BOOT_TARGET_DEVICES_USB(func)
#endif
#ifdef CONFIG_CMD_PXE
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif
#ifdef CONFIG_CMD_DHCP
#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif
/* FEL boot support, auto-execute boot.scr if a script address was provided */
#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
"bootcmd_fel=" \
@ -405,8 +417,8 @@ extern int soft_i2c_gpio_scl;
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
#define BOOTCMD_SUNXI_COMPAT \

16
include/reset.h
View File

@ -6,6 +6,7 @@
#ifndef _RESET_H
#define _RESET_H
#include <dm/ofnode.h>
#include <linux/errno.h>
/**
@ -102,6 +103,21 @@ struct reset_ctl_bulk {
int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl);
/**
* reset_get_by_index_nodev - Get/request a reset signal by integer index
* without a device.
*
* This is a version of reset_get_by_index() that does not use a device.
*
* @node: The client ofnode.
* @index: The index of the reset signal to request, within the client's
* list of reset signals.
* @reset_ctl A pointer to a reset control struct to initialize.
* @return 0 if OK, or a negative error code.
*/
int reset_get_by_index_nodev(ofnode node, int index,
struct reset_ctl *reset_ctl);
/**
* reset_get_bulk - Get/request all reset signals of a device.
*

21
test/dm/clk.c
View File

@ -4,12 +4,33 @@
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/clk.h>
#include <dm/test.h>
#include <linux/err.h>
#include <test/ut.h>
/* Base test of the clk uclass */
static int dm_test_clk_base(struct unit_test_state *uts)
{
struct udevice *dev;
struct clk clk_method1;
struct clk clk_method2;
/* Get the device using the clk device */
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
/* Get the same clk port in 2 different ways and compare */
ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
ut_asserteq(clk_method1.id, clk_method2.id);
return 0;
}
DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT);
static int dm_test_clk(struct unit_test_state *uts)
{
struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;

23
test/dm/reset.c
View File

@ -5,6 +5,7 @@
#include <common.h>
#include <dm.h>
#include <reset.h>
#include <dm/test.h>
#include <asm/reset.h>
#include <test/ut.h>
@ -15,6 +16,28 @@
/* This is the other reset phandle specifier handled by bulk */
#define OTHER_RESET_ID 2
/* Base test of the reset uclass */
static int dm_test_reset_base(struct unit_test_state *uts)
{
struct udevice *dev;
struct reset_ctl reset_method1;
struct reset_ctl reset_method2;
/* Get the device using the reset device */
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
&dev));
/* Get the same reset port in 2 different ways and compare */
ut_assertok(reset_get_by_index(dev, 1, &reset_method1));
ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1,
&reset_method2));
ut_asserteq(reset_method1.id, reset_method2.id);
return 0;
}
DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_FDT);
static int dm_test_reset(struct unit_test_state *uts)
{
struct udevice *dev_reset;