Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Wolfgang Denk
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CHANGELOG
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CHANGELOG
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commit 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7
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Author: Wolfgang Denk <wd@denx.de>
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Date: Tue Aug 14 09:47:27 2007 +0200
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Coding style cleanup; rebuild CHANGELOG
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commit 7f3f2bd2dc08e0b05e185662ca2e2d283757104a
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Author: Randy Vinson <rvinson@linuxbox.(none)>
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Date: Tue Feb 27 19:42:22 2007 -0700
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85xxCDS: Add make targets for legacy systems.
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The PCI ID select values on the Arcadia main board differ depending
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on the version of the hardware. The standard configuration supports
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Rev 3.1. The legacy target supports Rev 2.x.
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Signed-off-by Randy Vinson <rvinson@mvista.com>
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commit e41094c7e38177c755fbd9b182018069614f080d
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Author: Andy Fleming <afleming@freescale.com>
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Date: Tue Aug 14 01:50:09 2007 -0500
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85xxCDS: Enable the VIA PCI-to-ISA bridge.
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Author: Randy Vinson <rvinson@linuxbox.(none)>
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Enable the PCI-to-ISA bridge in the VIA Southbridge located on the
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Arcadia main board.
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Signed-off-by: Randy Vinson <rvinson@mvista.com>
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Signed-off-by: York Sun <yorksun@freescale.com>
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commit da9d4610d76e52c4d20a8f3d8433439a7fcf5b71
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Author: Andy Fleming <afleming@freescale.com>
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Date: Tue Aug 14 00:14:25 2007 -0500
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Add support for UEC to 8568
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Signed-off-by: Andy Fleming <afleming@freescale.com>
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commit c59e4091ffe0148398b9e9ff14a019ea038b7432
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Author: Haiying Wang <Haiying.Wang@freescale.com>
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Date: Tue Jun 19 14:18:34 2007 -0400
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Add PCI support for MPC8568MDS board
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This patch is against u-boot-mpc85xx.git of www.denx.com
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
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commit d111d6382c99fdea08c2312eeeae8786945e189a
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Author: Haiying Wang <Haiying.Wang@freescale.com>
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Date: Tue Jun 19 14:18:32 2007 -0400
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Empirically set cpo and clk_adjust for mpc85xx DDR2 support
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This patch is against u-boot-mpc85xx.git of www.denx.com
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Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
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both MPC8548CDS board and MPC8568MDS board, especially for supporting
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533MHz DDR2.
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Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
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DDR2 on all current board versions especially ver 1.92 or later to bring
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up.
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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commit 3db0bef59eab1155801618cef5c481e97553b597
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Author: Kumar Gala <galak@kernel.crashing.org>
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Date: Tue Aug 7 18:07:27 2007 -0500
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Use an absolute address when jumping out of 4k boot page
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On e500 when we leave the 4k boot page we should use an absolute address since
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we don't know where the board code may want us to be really running at.
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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commit 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a
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Author: Andy Fleming <afleming@freescale.com>
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Date: Mon Aug 13 14:49:59 2007 -0500
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MPC85xx BA bits not set for 3-bit bank address DIMM
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The current implementation does not set the number of bank address bits
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(BA) in the processor. The default assumes 2 logical bank bits. This
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works fine for a DIMM that uses devices with 4 internal banks (SPD
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byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
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devices with 8 internal banks (SPD byte17 = 0x8).
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Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
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commit 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1
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Author: Andy Fleming <afleming@freescale.com>
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Date: Mon Aug 13 14:38:06 2007 -0500
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Fix minor 85xx warnings
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Some patches had inserted warnings into the build:
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* mpc8560ads declared data without using it
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* cpu_init declared ecm and immap without using it in all CONFIGs
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* MPC8548CDS.h had its default filenames changed so that they contained
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"\m" in the paths. Made the defaults not Windows-specific (or
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anything-specific)
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Signed-off-by: Andy Fleming <afleming@freescale.com>
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commit f2cff6b104f82b993bef6086ce0c97159bbe1add
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Author: Ed Swarthout <Ed.Swarthout@freescale.com>
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Date: Fri Jul 27 01:50:52 2007 -0500
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8548cds PCIE support.
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Make the early L1 cache stack region guarded to prevent speculative
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fetches outside the locked range.
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Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions.
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init.S whitespace cleanup.
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Allow TEXT_BASE value to be specified on command line. This allows it
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to be set to 0xfffc0000 which cuts the uboot binary in half.
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Clear and enable lbc and ecm errors.
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Update last_busno in device-tree for pci and pcie.
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Remove load of obsolete cpu/mpc85xx/pci.0
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Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Acked-by: Andy Fleming <afleming@freescale.com>
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commit 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962
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Author: Ed Swarthout <Ed.Swarthout@freescale.com>
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Date: Fri Jul 27 01:50:51 2007 -0500
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8544ds PCIE support
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PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
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Enable LBC and ECM errors and clear error registers.
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Add tftpflash env var to get uboot from tftp server and flash it.
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Add pci/pcie convenience env vars to display register space:
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"run pcie3regs" to see all pcie3 ccsr registers
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"run pcie3cfg" to see all cfg registers
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Whitespace cleanup and MPC8544DS.h
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Enable CONFIG_INTERRUPTS.
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Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Acked-by: Andy Fleming <afleming@freescale.com>
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commit 61a21e980a7b9188424d04f1c265fdc5c21c7e85
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Author: Andy Fleming <afleming@freescale.com>
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Date: Tue Aug 14 01:34:21 2007 -0500
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85xx start.S cleanup and exception support
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From: Ed Swarthout <Ed.Swarthout@freescale.com>
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Support external interrupts from platform to eliminate system hangs.
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Define CONFIG_INTERRUPTS board configure option to enable.
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Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.
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Remove extra cpu initialization redundant with hardware initialization.
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Whitespace cleanup.
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Define and use _START_OFFSET consistent with other processors using
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ppc_asm.tmpl
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Move additional code from .text to boot page to make room for
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exception vectors at start of image.
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Handle Machine Check, External and Critical exceptions.
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Fix e500 machine check error determination in traps.c
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TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
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Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Acked-by: Andy Fleming <afleming@freescale.com>
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commit 7bd30fc4a6475b41d6679ae3aafc9fa505260c47
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Author: Andy Fleming <afleming@freescale.com>
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Date: Tue Aug 14 01:33:18 2007 -0500
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Add MPC8544DS README
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Signed-off-by: Andy Fleming <afleming@freescale.com>
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commit 40c7f9b0de4e300370adfc704128fa0f79a143b6
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Author: Ed Swarthout <Ed.Swarthout@freescale.com>
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Date: Fri Jul 27 01:50:48 2007 -0500
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85xx allow debugger to configure ddr.
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Only check for mpc8548 rev 1 when compiled for 8548.
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Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Acked-by: Andy Fleming <afleming@freescale.com>
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commit 29372ff38c5baab7d0e3a8c14fe11fa194a38704
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Author: Ed Swarthout <Ed.Swarthout@freescale.com>
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Date: Fri Jul 27 01:50:47 2007 -0500
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mpc85xx L2 cache reporting and SRAM relocation option.
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Allow debugger to override flash cs0/cs1 settings to enable alternate
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boot regions
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Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Acked-by: Andy Fleming <afleming@freescale.com>
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commit 41f0f8fb1ab92f0cba7d329de90070f822f8299f
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Author: Ed Swarthout <Ed.Swarthout@freescale.com>
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Date: Fri Jul 27 01:50:46 2007 -0500
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e500 needs ppc_asm.tmp MCK_EXCEPTION
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Always define MCK_EXCEPTION macro - so e500 can use it too.
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Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Acked-by: Andy Fleming <afleming@freescale.com>
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commit 53a5c424bf8655b7b4e2c305a441963259a26a81
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Author: David Updegraff <dave@cray.com>
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Date: Mon Jun 11 10:41:07 2007 -0500
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@ -98,7 +98,7 @@ Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
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After placing the DTB file in your TFTP disk area,
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After placing the DTB file in your TFTP disk area,
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you can download that dtb file using a command like:
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tftp 900000 mpc8544ds.dtb
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