Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

board/xilinx/microblaze-generic/xparameters.h

@@ -13,21 +13,10 @@
 
 #define XILINX_BOARD_NAME	microblaze-generic
 
-/* System Clock Frequency */
-#define XILINX_CLOCK_FREQ	100000000
-
 /* Microblaze is microblaze_0 */
 #define XILINX_USE_MSR_INSTR	1
 #define XILINX_FSL_NUMBER	3
 
-/* Interrupt controller is opb_intc_0 */
-#define XILINX_INTC_BASEADDR	0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS	6
-
-/* Timer pheriphery is opb_timer_1 */
-#define XILINX_TIMER_BASEADDR	0x41c00000
-#define XILINX_TIMER_IRQ	0
-
 /* GPIO is LEDs_4Bit*/
 #define XILINX_GPIO_BASEADDR	0x40000000
 

board/xilinx/zynq/board.c

@@ -98,6 +98,19 @@ int checkboard(void)
 }
 #endif
 
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+			ethaddr, 6))
+		printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+	return 0;
+}
+
 int dram_init(void)
 {
 	int node;

board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h

@@ -62,7 +62,7 @@ extern unsigned long *ps7_peripherals_init_data;
 #define USB0_FREQ  60000000
 #define USB1_FREQ  60000000
 #define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
+#define UART_FREQ  100000000
 #define SPI_FREQ  10000000
 #define I2C_FREQ  108333336
 #define WDT_FREQ  108333336
@@ -71,9 +71,10 @@ extern unsigned long *ps7_peripherals_init_data;
 #define PCAP_FREQ  200000000
 #define TPIU_FREQ  200000000
 #define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  175000000
-#define FPGA2_FREQ  12264151
-#define FPGA3_FREQ  100000000
+#define FPGA1_FREQ  142857132
+#define FPGA2_FREQ  200000000
+#define FPGA3_FREQ  50000000
+
 
 /* For delay calculation using global registers*/
 #define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200

board/xilinx/zynqmp/MAINTAINERS

@@ -1,7 +1,6 @@
-XILINX_ZYNQMP_EP BOARD
+XILINX_ZYNQMP BOARDS
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 F:	board/xilinx/zynqmp/
-F:	include/configs/xilinx_zynqmp.h
-F:	include/configs/xilinx_zynqmp_ep.h
-F:	configs/xilinx_zynqmp_ep_defconfig
+F:	include/configs/xilinx_zynqmp*
+F:	configs/xilinx_zynqmp*

board/xilinx/zynqmp/zynqmp.c

@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
 #include <asm/arch/clk.h>
@@ -50,12 +51,133 @@ int board_early_init_r(void)
 	return 0;
 }
 
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+			       const u32 *cell, int n)
+{
+	int i = 0, b, banks;
+	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+	int address_cells = fdt_address_cells(fdt, parent_offset);
+	int size_cells = fdt_size_cells(fdt, parent_offset);
+	char *p = buf;
+	phys_addr_t val;
+	phys_size_t vals;
+
+	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+	      __func__, address_cells, size_cells, buf, cell);
+
+	/* Check memory bank setup */
+	banks = n % (address_cells + size_cells);
+	if (banks)
+		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+		      n, address_cells, size_cells);
+
+	banks = n / (address_cells + size_cells);
+
+	for (b = 0; b < banks; b++) {
+		debug("%s: Bank #%d:\n", __func__, b);
+		if (address_cells == 2) {
+			val = cell[i + 1];
+			val <<= 32;
+			val |= cell[i];
+			val = fdt64_to_cpu(val);
+			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+			      __func__, val, p, &cell[i]);
+			*(phys_addr_t *)p = val;
+		} else {
+			debug("%s: addr32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_addr_t);
+		i += address_cells;
+
+		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+		      sizeof(phys_addr_t));
+
+		if (size_cells == 2) {
+			vals = cell[i + 1];
+			vals <<= 32;
+			vals |= cell[i];
+			vals = fdt64_to_cpu(vals);
+
+			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+			      __func__, vals, p, &cell[i]);
+			*(phys_size_t *)p = vals;
+		} else {
+			debug("%s: size32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_size_t);
+		i += size_cells;
+
+		debug("%s: ps=%p, i=%x, size=%zu\n",
+		      __func__, p, i, sizeof(phys_size_t));
+	}
+
+	/* Return the first address size */
+	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+	int bank;
+
+	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		debug("Bank #%d: start %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].start);
+		debug("Bank #%d: size %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].size);
+	}
+}
+
+int dram_init(void)
+{
+	int node, len;
+	const void *blob = gd->fdt_blob;
+	const u32 *cell;
+
+	memset(&tmp, 0, sizeof(tmp));
+
+	/* find or create "/memory" node. */
+	node = fdt_subnode_offset(blob, 0, "memory");
+	if (node < 0) {
+		printf("%s: Can't get memory node\n", __func__);
+		return node;
+	}
+
+	/* Get pointer to cells and lenght of it */
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell) {
+		printf("%s: Can't get reg property\n", __func__);
+		return -1;
+	}
+
+	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+	debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+
+	return 0;
+}
+#else
 int dram_init(void)
 {
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	return 0;
 }
+#endif
 
 void reset_cpu(ulong addr)
 {
@@ -64,6 +186,9 @@ void reset_cpu(ulong addr)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 void scsi_init(void)
 {
+#if defined(CONFIG_SATA_CEVA)
+	init_sata(0);
+#endif
 	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
 	scsi_scan(1);
 }