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imx: imx8mm_icore: Enable SPL_DM_SERIAL

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Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Peng Fan 2022-06-11 20:20:57 +08:00 committed by Stefano Babic
parent 37750505b9
commit 4ebb9a5898
4 changed files with 3 additions and 16 deletions
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14
board/engicam/imx8mm/spl.c
View File

@ -54,19 +54,11 @@ int board_fit_config_name_match(const char *name)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
return 0;
}
void board_init_f(ulong dummy)
@ -81,8 +73,6 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@ -92,6 +82,8 @@ void board_init_f(ulong dummy)
hang();
}
preloader_console_init();
enable_tzc380();
/* DDR initialization */

1
configs/imx8mm-icore-mx8mm-ctouch2_defconfig
View File

@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y

1
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
View File

@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y

3
include/configs/imx8mm_icore_mx8mm.h
View File

@ -54,9 +54,6 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0