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armv8: fsl-lsch2: enable snoopable sata read and write

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By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions.  This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Tang Yuantian
2016-08-08 15:07:20 +08:00
committed by York Sun
parent f0beb49290
commit 4de6ce1594
3 changed files with 7 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/cpu/armv8/fsl-layerscape/soc.c
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@@ -234,6 +234,7 @@ int sata_init(void)
#endif #endif
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA); ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0); scsi_scan(0);
@@ -337,7 +338,9 @@ void fsl_lsch2_early_init_f(void)
#endif #endif
/* Make SEC reads and writes snoopable */ /* Make SEC reads and writes snoopable */
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP); SCFG_SNPCNFGCR_SECWRSNP |
SCFG_SNPCNFGCR_SATARDSNP |
SCFG_SNPCNFGCR_SATAWRSNP);
/* /*
* Enable snoop requests and DVM message requests for * Enable snoop requests and DVM message requests for

2
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@@ -335,6 +335,8 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
/* Supplemental Configuration Unit */ /* Supplemental Configuration Unit */
struct ccsr_scfg { struct ccsr_scfg {

1
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@@ -61,6 +61,7 @@ struct cpu_type {
/* ahci port register default value */ /* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe #define AHCI_PORT_PHY_1_CFG 0xa003fffe
#define AHCI_PORT_TRANS_CFG 0x08000029 #define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
/* AHCI (sata) register map */ /* AHCI (sata) register map */
struct ccsr_ahci { struct ccsr_ahci {