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board: fsl: lx2160ardb: invert AQR107 pins polarity

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AQR107 PHYs interrupt pins are active-low, while the GIC expects a
level-high signal.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Florin Chiculita 2019-04-22 11:57:47 +03:00 committed by Prabhakar Kushwaha
parent d2ebc38236
commit 4dde343d7e
2 changed files with 9 additions and 0 deletions
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8
board/freescale/lx2160a/lx2160a.c
View File

@ -449,12 +449,20 @@ unsigned long get_board_ddr_clk(void)
int board_init(void)
{
#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
/* invert AQR107 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif

1
include/configs/lx2160ardb.h
View File

@ -60,6 +60,7 @@
#define AQR107_PHY_ADDR1 0x04
#define AQR107_PHY_ADDR2 0x05
#define AQR107_IRQ_MASK 0x0C
#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0