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common: board_r: support enable_caches for RISC-V

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The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Zong Li
2021-09-01 15:01:40 +08:00
committed by Leo Yu-Chi Liang
parent 43a2183928
commit 4d4222d074
2 changed files with 6 additions and 2 deletions
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4
arch/riscv/lib/cache.c
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@@ -70,3 +70,7 @@ __weak int dcache_status(void)
{ {
return 0; return 0;
} }
__weak void enable_caches(void)
{
}

4
common/board_r.c
View File

@@ -114,7 +114,7 @@ static int initr_reloc(void)
return 0; return 0;
} }
#ifdef CONFIG_ARM #if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
/* /*
* Some of these functions are needed purely because the functions they * Some of these functions are needed purely because the functions they
* call return void. If we change them to return 0, these stubs can go away. * call return void. If we change them to return 0, these stubs can go away.
@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
initr_trace, initr_trace,
initr_reloc, initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */ /* TODO: could x86/PPC have this also perhaps? */
#ifdef CONFIG_ARM #if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
initr_caches, initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
* A temporary mapping of IFC high region is since removed, * A temporary mapping of IFC high region is since removed,