Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig
This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_OOBFREE CONFIG_SYS_NAND_MAX_ECCPOS Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
b41641d52e
commit
4d3495deb6
@ -25,6 +25,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0x100
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CONFIG_SYS_NAND_OOBSIZE=0x100
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CONFIG_SYS_NAND_MAX_ECCPOS=1664
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CONFIG_AXP_ALDO3_VOLT=3300
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CONFIG_AXP_ALDO3_VOLT=3300
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CONFIG_AXP_ALDO4_VOLT=3300
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CONFIG_AXP_ALDO4_VOLT=3300
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CONFIG_CONS_INDEX=2
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CONFIG_CONS_INDEX=2
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@ -20,6 +20,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_MAX_ECCPOS=1664
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CONFIG_AXP_DLDO1_VOLT=3300
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CONFIG_AXP_DLDO1_VOLT=3300
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CONFIG_AXP_ELDO2_VOLT=1800
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CONFIG_AXP_ELDO2_VOLT=1800
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CONFIG_CONS_INDEX=5
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CONFIG_CONS_INDEX=5
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@ -81,6 +81,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=56
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CONFIG_MII=y
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CONFIG_MII=y
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CONFIG_DRIVER_TI_EMAC=y
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CONFIG_DRIVER_TI_EMAC=y
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CONFIG_DRIVER_TI_EMAC_USE_RMII=y
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CONFIG_DRIVER_TI_EMAC_USE_RMII=y
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@ -83,6 +83,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHYLIB_10G=y
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@ -69,6 +69,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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@ -72,6 +72,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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@ -104,6 +104,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_REALTEK=y
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@ -92,6 +92,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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@ -91,6 +91,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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@ -72,6 +72,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -75,6 +75,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -95,6 +95,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -95,6 +95,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -71,6 +71,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -77,6 +77,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -74,6 +74,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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@ -77,6 +77,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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@ -91,6 +91,8 @@ CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -71,6 +71,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -85,6 +85,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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@ -76,6 +76,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB=y
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@ -79,6 +79,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB=y
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@ -100,6 +100,8 @@ CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_PHY_CORTINA=y
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@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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@ -81,6 +81,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_MAX_OOBFREE=2
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CONFIG_SYS_NAND_MAX_ECCPOS=256
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_MTD_RAW_NAND=y
|
CONFIG_MTD_RAW_NAND=y
|
||||||
CONFIG_NAND_FSL_IFC=y
|
CONFIG_NAND_FSL_IFC=y
|
||||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||||
|
CONFIG_SYS_NAND_MAX_OOBFREE=2
|
||||||
|
CONFIG_SYS_NAND_MAX_ECCPOS=256
|
||||||
CONFIG_DM_SPI_FLASH=y
|
CONFIG_DM_SPI_FLASH=y
|
||||||
# CONFIG_SPI_FLASH_BAR is not set
|
# CONFIG_SPI_FLASH_BAR is not set
|
||||||
CONFIG_SPI_FLASH_SPANSION=y
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
@ -80,6 +80,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
|
|||||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_SYS_NAND_MAX_OOBFREE=2
|
||||||
|
CONFIG_SYS_NAND_MAX_ECCPOS=56
|
||||||
CONFIG_SMC911X=y
|
CONFIG_SMC911X=y
|
||||||
CONFIG_SMC911X_32_BIT=y
|
CONFIG_SMC911X_32_BIT=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
|
@ -88,6 +88,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
|
|||||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_SYS_NAND_MAX_OOBFREE=2
|
||||||
|
CONFIG_SYS_NAND_MAX_ECCPOS=56
|
||||||
CONFIG_SMC911X=y
|
CONFIG_SMC911X=y
|
||||||
CONFIG_SMC911X_32_BIT=y
|
CONFIG_SMC911X_32_BIT=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
|
@ -79,6 +79,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
|
|||||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_SYS_NAND_MAX_OOBFREE=2
|
||||||
|
CONFIG_SYS_NAND_MAX_ECCPOS=56
|
||||||
CONFIG_SMC911X=y
|
CONFIG_SMC911X=y
|
||||||
CONFIG_SMC911X_32_BIT=y
|
CONFIG_SMC911X_32_BIT=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
|
@ -89,6 +89,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40
|
|||||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_SYS_NAND_MAX_OOBFREE=2
|
||||||
|
CONFIG_SYS_NAND_MAX_ECCPOS=56
|
||||||
CONFIG_SMC911X=y
|
CONFIG_SMC911X=y
|
||||||
CONFIG_SMC911X_32_BIT=y
|
CONFIG_SMC911X_32_BIT=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
|
@ -99,16 +99,6 @@ Configuration Options:
|
|||||||
CONFIG_CMD_NAND_TORTURE
|
CONFIG_CMD_NAND_TORTURE
|
||||||
Enables the torture command (see description of this command below).
|
Enables the torture command (see description of this command below).
|
||||||
|
|
||||||
CONFIG_SYS_NAND_MAX_ECCPOS
|
|
||||||
If specified, overrides the maximum number of ECC bytes
|
|
||||||
supported. Useful for reducing image size, especially with SPL.
|
|
||||||
This must be at least 48 if nand_base.c is used.
|
|
||||||
|
|
||||||
CONFIG_SYS_NAND_MAX_OOBFREE
|
|
||||||
If specified, overrides the maximum number of free OOB regions
|
|
||||||
supported. Useful for reducing image size, especially with SPL.
|
|
||||||
This must be at least 2 if nand_base.c is used.
|
|
||||||
|
|
||||||
CONFIG_SYS_NAND_MAX_CHIPS
|
CONFIG_SYS_NAND_MAX_CHIPS
|
||||||
The maximum number of NAND chips per device to be supported.
|
The maximum number of NAND chips per device to be supported.
|
||||||
|
|
||||||
|
@ -212,6 +212,24 @@ config SYS_MAX_FLASH_BANKS_DETECT
|
|||||||
|
|
||||||
source "drivers/mtd/nand/Kconfig"
|
source "drivers/mtd/nand/Kconfig"
|
||||||
|
|
||||||
|
config SYS_NAND_MAX_OOBFREE
|
||||||
|
int "Maximum number of free OOB regions supported"
|
||||||
|
depends on SAMSUNG_ONENAND || MTD_RAW_NAND
|
||||||
|
range 2 32
|
||||||
|
default 32
|
||||||
|
help
|
||||||
|
Set the maximum number of free OOB regions supported. Useful for
|
||||||
|
reducing image size, especially with SPL.
|
||||||
|
|
||||||
|
config SYS_NAND_MAX_ECCPOS
|
||||||
|
int "Maximum number of ECC bytes supported"
|
||||||
|
depends on SAMSUNG_ONENAND || MTD_RAW_NAND
|
||||||
|
range 48 2147483647
|
||||||
|
default 680
|
||||||
|
help
|
||||||
|
Set the maximum number of ECC bytes supported. Useful for reducing
|
||||||
|
image size, especially with SPL.
|
||||||
|
|
||||||
config SYS_NAND_MAX_CHIPS
|
config SYS_NAND_MAX_CHIPS
|
||||||
int "NAND max chips"
|
int "NAND max chips"
|
||||||
depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
|
depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
|
||||||
|
@ -197,8 +197,6 @@
|
|||||||
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||||
|
|
||||||
/* NAND Flash on IFC */
|
/* NAND Flash on IFC */
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||||
|
|
||||||
|
@ -25,8 +25,6 @@
|
|||||||
|
|
||||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||||
#define CONFIG_SYS_NAND_ECCBYTES 13
|
#define CONFIG_SYS_NAND_ECCBYTES 13
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
|
|
||||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
|
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
|
||||||
/* NAND block size is 128 KiB. Synchronize these values with
|
/* NAND block size is 128 KiB. Synchronize these values with
|
||||||
* corresponding Device Tree entries in Linux:
|
* corresponding Device Tree entries in Linux:
|
||||||
|
@ -69,9 +69,6 @@
|
|||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
||||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||||
|
@ -53,9 +53,6 @@
|
|||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
||||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||||
|
@ -70,9 +70,6 @@
|
|||||||
CONFIG_SYS_FLASH_BASE + 0x40000000}
|
CONFIG_SYS_FLASH_BASE + 0x40000000}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
||||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||||
|
@ -67,9 +67,6 @@
|
|||||||
CONFIG_SYS_FLASH_BASE + 0x40000000}
|
CONFIG_SYS_FLASH_BASE + 0x40000000}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
||||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||||
|
@ -26,8 +26,6 @@
|
|||||||
|
|
||||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||||
#define CONFIG_SYS_NAND_ECCBYTES 13
|
#define CONFIG_SYS_NAND_ECCBYTES 13
|
||||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Environment information */
|
/* Environment information */
|
||||||
|
@ -71,10 +71,6 @@
|
|||||||
#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
|
#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
|
||||||
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
|
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
|
||||||
|
|
||||||
#ifdef CONFIG_NAND_SUNXI
|
|
||||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* mmc config */
|
/* mmc config */
|
||||||
#define CONFIG_MMC_SUNXI_SLOT 0
|
#define CONFIG_MMC_SUNXI_SLOT 0
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user