pinctrl: mtmips: add support for MediaTek MT7621 SoC
This patch adds pinctrl support for MediaTek MT7621 SoC. The MT7621 SoC supports pinconf, but it is not the same as mt7628. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Daniel Schwierzeck
parent
daf4ce6b5e
commit
4d30111cea
@ -12,6 +12,15 @@ config PINCTRL_MT7620
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The driver is controlled by a device tree node which contains
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the pin mux functions for each available pin groups.
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config PINCTRL_MT7621
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bool "MediaTek MT7621 pin control driver"
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select PINCTRL_MTMIPS
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depends on SOC_MT7621 && PINCTRL_GENERIC
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help
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Support pin multiplexing control on MediaTek MT7621.
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The driver is controlled by a device tree node which contains
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the pin mux functions for each available pin groups.
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config PINCTRL_MT7628
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bool "MediaTek MT7628 pin control driver"
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select PINCTRL_MTMIPS
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@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-mtmips-common.o
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# SoC Drivers
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obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
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obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
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obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o
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306
drivers/pinctrl/mtmips/pinctrl-mt7621.c
Normal file
306
drivers/pinctrl/mtmips/pinctrl-mt7621.c
Normal file
@ -0,0 +1,306 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include "pinctrl-mtmips-common.h"
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#define SYSC_MAP_SIZE 0x100
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#define PAD_UART1_GPIO0_OFS 0x00
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#define PAD_UART3_I2C_OFS 0x04
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#define PAD_UART2_JTAG_OFS 0x08
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#define PAD_PERST_WDT_OFS 0x0c
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#define PAD_RGMII2_MDIO_OFS 0x10
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#define PAD_SDXC_SPI_OFS 0x14
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#define GPIOMODE_OFS 0x18
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#define PAD_BOPT_ESWINT_OFS 0x28
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#define ESWINT_SHIFT 20
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#define SDXC_SHIFT 18
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#define SPI_SHIFT 16
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#define RGMII2_SHIFT 15
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#define RGMII1_SHIFT 14
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#define MDIO_SHIFT 12
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#define PERST_SHIFT 10
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#define WDT_SHIFT 8
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#define JTAG_SHIFT 7
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#define UART2_SHIFT 5
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#define UART3_SHIFT 3
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#define I2C_SHIFT 2
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#define UART1_SHIFT 1
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#define GPIO0_SHIFT 0 /* Dummy */
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#define GM4_MASK 3
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#define E4_E2_M 0x03
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#define E4_E2_S 4
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#define PULL_UP BIT(3)
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#define PULL_DOWN BIT(2)
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#define SMT BIT(1)
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#define SR BIT(0)
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struct mt7621_pinctrl_priv {
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struct mtmips_pinctrl_priv mp;
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};
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#if CONFIG_IS_ENABLED(PINMUX)
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static const struct mtmips_pmx_func esw_int_grp[] = {
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FUNC("gpio", 1),
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FUNC("esw int", 0),
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};
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static const struct mtmips_pmx_func sdxc_grp[] = {
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FUNC("nand", 2),
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FUNC("gpio", 1),
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FUNC("sdxc", 0),
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};
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static const struct mtmips_pmx_func spi_grp[] = {
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FUNC("nand", 2),
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FUNC("gpio", 1),
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FUNC("spi", 0),
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};
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static const struct mtmips_pmx_func rgmii2_grp[] = {
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FUNC("gpio", 1),
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FUNC("rgmii", 0),
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};
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static const struct mtmips_pmx_func rgmii1_grp[] = {
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FUNC("gpio", 1),
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FUNC("rgmii", 0),
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};
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static const struct mtmips_pmx_func mdio_grp[] = {
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FUNC("gpio", 1),
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FUNC("mdio", 0),
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};
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static const struct mtmips_pmx_func perst_grp[] = {
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FUNC("refclk", 2),
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FUNC("gpio", 1),
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FUNC("pcie reset", 0),
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};
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static const struct mtmips_pmx_func wdt_grp[] = {
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FUNC("refclk", 2),
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FUNC("gpio", 1),
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FUNC("wdt rst", 0),
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};
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static const struct mtmips_pmx_func jtag_grp[] = {
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FUNC("gpio", 1),
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FUNC("jtag", 0),
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};
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static const struct mtmips_pmx_func uart2_grp[] = {
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FUNC("spdif", 3),
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FUNC("pcm", 2),
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FUNC("gpio", 1),
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FUNC("uart", 0),
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};
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static const struct mtmips_pmx_func uart3_grp[] = {
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FUNC("spdif", 3),
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FUNC("i2s", 2),
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FUNC("gpio", 1),
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FUNC("uart", 0),
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};
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static const struct mtmips_pmx_func i2c_grp[] = {
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FUNC("gpio", 1),
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FUNC("i2c", 0),
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};
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static const struct mtmips_pmx_func uart1_grp[] = {
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FUNC("gpio", 1),
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FUNC("uart", 0),
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};
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static const struct mtmips_pmx_func gpio0_grp[] = {
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FUNC("gpio", 0),
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};
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static const struct mtmips_pmx_group mt7621_pmx_data[] = {
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GRP_PCONF("esw int", esw_int_grp, GPIOMODE_OFS, ESWINT_SHIFT, 1,
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PAD_BOPT_ESWINT_OFS, 0),
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GRP_PCONF("sdxc", sdxc_grp, GPIOMODE_OFS, SDXC_SHIFT, GM4_MASK,
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PAD_SDXC_SPI_OFS, 16),
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GRP_PCONF("spi", spi_grp, GPIOMODE_OFS, SPI_SHIFT, GM4_MASK,
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PAD_SDXC_SPI_OFS, 0),
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GRP_PCONF("rgmii2", rgmii2_grp, GPIOMODE_OFS, RGMII2_SHIFT, 1,
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PAD_RGMII2_MDIO_OFS, 16),
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GRP("rgmii1", rgmii1_grp, GPIOMODE_OFS, RGMII1_SHIFT, 1),
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GRP_PCONF("mdio", mdio_grp, GPIOMODE_OFS, MDIO_SHIFT, GM4_MASK,
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PAD_RGMII2_MDIO_OFS, 0),
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GRP_PCONF("pcie reset", perst_grp, GPIOMODE_OFS, PERST_SHIFT, GM4_MASK,
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PAD_PERST_WDT_OFS, 16),
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GRP_PCONF("wdt", wdt_grp, GPIOMODE_OFS, WDT_SHIFT, GM4_MASK,
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PAD_PERST_WDT_OFS, 0),
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GRP_PCONF("jtag", jtag_grp, GPIOMODE_OFS, JTAG_SHIFT, 1,
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PAD_UART2_JTAG_OFS, 16),
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GRP_PCONF("uart2", uart2_grp, GPIOMODE_OFS, UART2_SHIFT, GM4_MASK,
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PAD_UART2_JTAG_OFS, 0),
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GRP_PCONF("uart3", uart3_grp, GPIOMODE_OFS, UART3_SHIFT, GM4_MASK,
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PAD_UART3_I2C_OFS, 16),
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GRP_PCONF("i2c", i2c_grp, GPIOMODE_OFS, I2C_SHIFT, 1,
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PAD_UART3_I2C_OFS, 0),
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GRP_PCONF("uart1", uart1_grp, GPIOMODE_OFS, UART1_SHIFT, 1,
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PAD_UART1_GPIO0_OFS, 16),
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GRP_PCONF("gpio0", gpio0_grp, GPIOMODE_OFS, GPIO0_SHIFT, 1,
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PAD_UART1_GPIO0_OFS, 0),
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};
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static int mt7621_get_groups_count(struct udevice *dev)
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{
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return ARRAY_SIZE(mt7621_pmx_data);
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}
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static const char *mt7621_get_group_name(struct udevice *dev,
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unsigned int selector)
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{
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return mt7621_pmx_data[selector].name;
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}
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#endif /* CONFIG_IS_ENABLED(PINMUX) */
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#if CONFIG_IS_ENABLED(PINCONF)
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static const struct pinconf_param mt7621_conf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
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{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
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{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
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{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
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{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
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};
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static const u32 mt7621_pconf_drv_strength_tbl[] = {2, 4, 6, 8};
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static int mt7621_pinconf_group_set(struct udevice *dev,
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unsigned int group_selector,
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unsigned int param, unsigned int arg)
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{
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struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
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const struct mtmips_pmx_group *grp = &mt7621_pmx_data[group_selector];
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u32 clr = 0, set = 0;
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int i;
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if (!grp->pconf_avail)
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return 0;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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clr = PULL_UP | PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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clr = PULL_DOWN;
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set = PULL_UP;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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clr = PULL_UP;
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set = PULL_DOWN;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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if (arg)
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set = SMT;
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else
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clr = SMT;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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for (i = 0; i < ARRAY_SIZE(mt7621_pconf_drv_strength_tbl); i++)
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if (mt7621_pconf_drv_strength_tbl[i] == arg)
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break;
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if (i >= ARRAY_SIZE(mt7621_pconf_drv_strength_tbl))
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return -EINVAL;
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clr = E4_E2_M << E4_E2_S;
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set = i << E4_E2_S;
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break;
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case PIN_CONFIG_SLEW_RATE:
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if (arg)
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set = SR;
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else
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clr = SR;
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break;
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default:
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return -EINVAL;
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}
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mtmips_pinctrl_reg_set(&priv->mp, grp->pconf_reg, grp->pconf_shift,
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clr, set);
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return 0;
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}
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#endif
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static int mt7621_pinctrl_probe(struct udevice *dev)
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{
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struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
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int ret = 0;
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#if CONFIG_IS_ENABLED(PINMUX)
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ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7621_pmx_data),
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mt7621_pmx_data);
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#endif /* CONFIG_IS_ENABLED(PINMUX) */
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return ret;
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}
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static int mt7621_pinctrl_of_to_plat(struct udevice *dev)
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{
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struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
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priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);
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if (!priv->mp.base)
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return -EINVAL;
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return 0;
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}
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static const struct pinctrl_ops mt7621_pinctrl_ops = {
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#if CONFIG_IS_ENABLED(PINMUX)
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.get_groups_count = mt7621_get_groups_count,
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.get_group_name = mt7621_get_group_name,
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.get_functions_count = mtmips_get_functions_count,
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.get_function_name = mtmips_get_function_name,
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.pinmux_group_set = mtmips_pinmux_group_set,
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#endif /* CONFIG_IS_ENABLED(PINMUX) */
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#if CONFIG_IS_ENABLED(PINCONF)
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.pinconf_num_params = ARRAY_SIZE(mt7621_conf_params),
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.pinconf_params = mt7621_conf_params,
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.pinconf_group_set = mt7621_pinconf_group_set,
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#endif /* CONFIG_IS_ENABLED(PINCONF) */
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.set_state = pinctrl_generic_set_state,
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};
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static const struct udevice_id mt7621_pinctrl_ids[] = {
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{ .compatible = "mediatek,mt7621-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(mt7621_pinctrl) = {
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.name = "mt7621-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = mt7621_pinctrl_ids,
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.of_to_plat = mt7621_pinctrl_of_to_plat,
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.ops = &mt7621_pinctrl_ops,
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.probe = mt7621_pinctrl_probe,
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.priv_auto = sizeof(struct mt7621_pinctrl_priv),
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};
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@ -13,8 +13,8 @@
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#include "pinctrl-mtmips-common.h"
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static void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
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u32 reg, u32 shift, u32 mask, u32 value)
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void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
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u32 reg, u32 shift, u32 mask, u32 value)
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{
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u32 val;
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@ -22,6 +22,10 @@ struct mtmips_pmx_group {
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u32 shift;
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char mask;
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int pconf_avail;
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u32 pconf_reg;
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u32 pconf_shift;
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int nfuncs;
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const struct mtmips_pmx_func *funcs;
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};
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@ -42,6 +46,14 @@ struct mtmips_pinctrl_priv {
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{ .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
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.funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs) }
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#define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \
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{ .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
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.funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs), .pconf_avail = 1, \
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.pconf_reg = (_pconf_reg), .pconf_shift = (_pconf_shift) }
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void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
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u32 reg, u32 shift, u32 mask, u32 value);
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int mtmips_get_functions_count(struct udevice *dev);
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const char *mtmips_get_function_name(struct udevice *dev,
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unsigned int selector);
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