arm: Remove mx53evk board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
397a43dc56
commit
4d24862848
@ -52,11 +52,6 @@ config TARGET_MX53CX9020
|
||||
select MX53
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_MX53EVK
|
||||
bool "Support mx53evk"
|
||||
select BOARD_LATE_INIT
|
||||
select MX53
|
||||
|
||||
config TARGET_MX53LOCO
|
||||
bool "Support mx53loco"
|
||||
select BOARD_LATE_INIT
|
||||
@ -83,7 +78,6 @@ config SYS_SOC
|
||||
|
||||
source "board/beckhoff/mx53cx9020/Kconfig"
|
||||
source "board/freescale/mx51evk/Kconfig"
|
||||
source "board/freescale/mx53evk/Kconfig"
|
||||
source "board/freescale/mx53loco/Kconfig"
|
||||
source "board/ge/mx53ppd/Kconfig"
|
||||
source "board/inversepath/usbarmory/Kconfig"
|
||||
|
||||
@ -1,15 +0,0 @@
|
||||
if TARGET_MX53EVK
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx53evk"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx5"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx53evk"
|
||||
|
||||
endif
|
||||
@ -1,6 +0,0 @@
|
||||
MX53EVK BOARD
|
||||
M: Jason Liu <jason.hui.liu@nxp.com>
|
||||
S: Maintained
|
||||
F: board/freescale/mx53evk/
|
||||
F: include/configs/mx53evk.h
|
||||
F: configs/mx53evk_defconfig
|
||||
@ -1,7 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2010 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y := mx53evk.o
|
||||
@ -1,97 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C Copyright 2009
|
||||
* Stefano Babic DENX Software Engineering sbabic@denx.de.
|
||||
*
|
||||
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
/* Setting IOMUXC */
|
||||
DATA 4 0x53fa8554 0x00200000
|
||||
DATA 4 0x53fa8560 0x00200000
|
||||
DATA 4 0x53fa8594 0x00200000
|
||||
DATA 4 0x53fa8584 0x00200000
|
||||
DATA 4 0x53fa8558 0x00200040
|
||||
DATA 4 0x53fa8568 0x00200040
|
||||
DATA 4 0x53fa8590 0x00200040
|
||||
DATA 4 0x53fa857c 0x00200040
|
||||
DATA 4 0x53fa8564 0x00200040
|
||||
DATA 4 0x53fa8580 0x00200040
|
||||
DATA 4 0x53fa8570 0x00200000
|
||||
DATA 4 0x53fa8578 0x00200000
|
||||
DATA 4 0x53fa872c 0x00200000
|
||||
DATA 4 0x53fa8728 0x00200000
|
||||
DATA 4 0x53fa871c 0x00200000
|
||||
DATA 4 0x53fa8718 0x00200000
|
||||
DATA 4 0x53fa8574 0x00280000
|
||||
DATA 4 0x53fa8588 0x00280000
|
||||
DATA 4 0x53fa86f0 0x00280000
|
||||
DATA 4 0x53fa8720 0x00280000
|
||||
DATA 4 0x53fa86fc 0x00000000
|
||||
DATA 4 0x53fa86f4 0x00000200
|
||||
DATA 4 0x53fa8714 0x00000000
|
||||
DATA 4 0x53fa8724 0x06000000
|
||||
DATA 4 0x63fd9088 0x34333936
|
||||
DATA 4 0x63fd9090 0x49434942
|
||||
DATA 4 0x63fd90F8 0x00000800
|
||||
DATA 4 0x63fd907c 0x01350138
|
||||
DATA 4 0x63fd9080 0x01380139
|
||||
DATA 4 0x63fd9018 0x00001710
|
||||
DATA 4 0x63fd9000 0xc4110000
|
||||
DATA 4 0x63fd900C 0x4d5122d2
|
||||
DATA 4 0x63fd9010 0x92d18a22
|
||||
DATA 4 0x63fd9014 0x00c70092
|
||||
DATA 4 0x63fd902c 0x000026d2
|
||||
DATA 4 0x63fd9030 0x009f000e
|
||||
DATA 4 0x63fd9008 0x12272000
|
||||
DATA 4 0x63fd9004 0x00030012
|
||||
DATA 4 0x63fd901c 0x04008010
|
||||
DATA 4 0x63fd901c 0x00008032
|
||||
DATA 4 0x63fd901c 0x00008033
|
||||
DATA 4 0x63fd901c 0x00008031
|
||||
DATA 4 0x63fd901c 0x0b5280b0
|
||||
DATA 4 0x63fd901c 0x04008010
|
||||
DATA 4 0x63fd901c 0x00008020
|
||||
DATA 4 0x63fd901c 0x00008020
|
||||
DATA 4 0x63fd901c 0x0a528030
|
||||
DATA 4 0x63fd901c 0x03c68031
|
||||
DATA 4 0x63fd901c 0x00448031
|
||||
DATA 4 0x63fd901c 0x04008018
|
||||
DATA 4 0x63fd901c 0x0000803a
|
||||
DATA 4 0x63fd901c 0x0000803b
|
||||
DATA 4 0x63fd901c 0x00008039
|
||||
DATA 4 0x63fd901c 0x0b528138
|
||||
DATA 4 0x63fd901c 0x04008018
|
||||
DATA 4 0x63fd901c 0x00008028
|
||||
DATA 4 0x63fd901c 0x00008028
|
||||
DATA 4 0x63fd901c 0x0a528038
|
||||
DATA 4 0x63fd901c 0x03c68039
|
||||
DATA 4 0x63fd901c 0x00448039
|
||||
DATA 4 0x63fd9020 0x00005800
|
||||
DATA 4 0x63fd9058 0x00033335
|
||||
DATA 4 0x63fd901c 0x00000000
|
||||
DATA 4 0x63fd9040 0x05380003
|
||||
DATA 4 0x53fa8004 0x00194005
|
||||
@ -1,270 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2010 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux-mx53.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <power/pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <mc13892.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t uart_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_HYS | PAD_CTL_ODE)
|
||||
|
||||
static void setup_i2c(unsigned int port_number)
|
||||
{
|
||||
static const iomux_v3_cfg_t i2c1_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
|
||||
};
|
||||
|
||||
static const iomux_v3_cfg_t i2c2_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
|
||||
};
|
||||
|
||||
switch (port_number) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(i2c1_pads,
|
||||
ARRAY_SIZE(i2c1_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(i2c2_pads,
|
||||
ARRAY_SIZE(i2c2_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: Wrong I2C port number\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void power_init(void)
|
||||
{
|
||||
unsigned int val;
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
|
||||
ret = pmic_init(I2C_0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
p = pmic_get("FSL_PMIC");
|
||||
if (!p)
|
||||
return;
|
||||
|
||||
/* Set VDDA to 1.25V */
|
||||
pmic_reg_read(p, REG_SW_2, &val);
|
||||
val &= ~SWX_OUT_MASK;
|
||||
val |= SWX_OUT_1_25;
|
||||
pmic_reg_write(p, REG_SW_2, val);
|
||||
|
||||
/*
|
||||
* Need increase VCC and VDDA to 1.3V
|
||||
* according to MX53 IC TO2 datasheet.
|
||||
*/
|
||||
if (is_soc_rev(CHIP_REV_2_0) == 0) {
|
||||
/* Set VCC to 1.3V for TO2 */
|
||||
pmic_reg_read(p, REG_SW_1, &val);
|
||||
val &= ~SWX_OUT_MASK;
|
||||
val |= SWX_OUT_1_30;
|
||||
pmic_reg_write(p, REG_SW_1, val);
|
||||
|
||||
/* Set VDDA to 1.3V for TO2 */
|
||||
pmic_reg_read(p, REG_SW_2, &val);
|
||||
val &= ~SWX_OUT_MASK;
|
||||
val |= SWX_OUT_1_30;
|
||||
pmic_reg_write(p, REG_SW_2, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t fec_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
|
||||
PAD_CTL_HYS | PAD_CTL_PKE),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
struct fsl_esdhc_cfg esdhc_cfg[2] = {
|
||||
{MMC_SDHC1_BASE_ADDR},
|
||||
{MMC_SDHC3_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret;
|
||||
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
|
||||
gpio_direction_input(IMX_GPIO_NR(3, 11));
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
|
||||
gpio_direction_input(IMX_GPIO_NR(3, 13));
|
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
|
||||
else
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP)
|
||||
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_DSE_HIGH)
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t sd1_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
|
||||
MX53_PAD_EIM_DA13__GPIO3_13,
|
||||
};
|
||||
|
||||
static const iomux_v3_cfg_t sd2_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
|
||||
SD_CMD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
|
||||
MX53_PAD_EIM_DA11__GPIO3_11,
|
||||
};
|
||||
|
||||
u32 index;
|
||||
int ret;
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(sd1_pads,
|
||||
ARRAY_SIZE(sd1_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(sd2_pads,
|
||||
ARRAY_SIZE(sd2_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more ESDHC controller"
|
||||
"(%d) as supported by the board(2)\n",
|
||||
CONFIG_SYS_FSL_ESDHC_NUM);
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
setup_iomux_fec();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
|
||||
{"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
setup_i2c(1);
|
||||
power_init();
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX53EVK\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,25 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX5=y
|
||||
CONFIG_SYS_TEXT_BASE=0x77800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x60000
|
||||
CONFIG_TARGET_MX53EVK=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,116 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the MX53-EVK Freescale board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
#define CONFIG_SYS_FSL_CLK
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
/* PMIC Configs */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_FSL
|
||||
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
|
||||
#define CONFIG_POWER_FSL_MC13892
|
||||
#define CONFIG_RTC_MC13XXX
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 2
|
||||
|
||||
/* Eth Configs */
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
/* Command definition */
|
||||
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
|
||||
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=2\0" \
|
||||
"mmcroot=/dev/mmcblk0p3 rw\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm\0" \
|
||||
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"dhcp ${uimage}; bootm\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* environment organization */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user