rockchip: rk3066: add sdram driver
Add rockchip rk3066 sdram driver Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Paweł Jarosz
Kever Yang
parent
086863c982
commit
4b957e7ff5
@ -5,6 +5,7 @@
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obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
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obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
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obj-$(CONFIG_ROCKCHIP_RK3066) = sdram_rk3066.o
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obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
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obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
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obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
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892
drivers/ram/rockchip/sdram_rk3066.c
Normal file
892
drivers/ram/rockchip/sdram_rk3066.c
Normal file
@ -0,0 +1,892 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* (C) Copyright 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*
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* Adapted from the very similar rk3188 ddr init.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3066.h>
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#include <asm/arch-rockchip/ddr_rk3188.h>
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#include <asm/arch-rockchip/grf_rk3066.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/pmu_rk3188.h>
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#include <asm/arch-rockchip/sdram_rk3288.h>
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#include <asm/arch-rockchip/sdram.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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struct rk3066_dmc_chan_info {
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struct rk3288_ddr_pctl *pctl;
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struct rk3288_ddr_publ *publ;
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struct rk3188_msch *msch;
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};
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struct rk3066_dmc_dram_info {
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struct rk3066_dmc_chan_info chan[1];
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struct ram_info info;
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struct clk ddr_clk;
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struct rk3066_cru *cru;
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struct rk3066_grf *grf;
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struct rk3066_sgrf *sgrf;
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struct rk3188_pmu *pmu;
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};
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struct rk3066_dmc_sdram_params {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3066_dmc of_plat;
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#endif
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struct rk3288_sdram_channel ch[2];
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struct rk3288_sdram_pctl_timing pctl_timing;
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struct rk3288_sdram_phy_timing phy_timing;
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struct rk3288_base_params base;
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int num_channels;
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struct regmap *map;
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};
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const int rk3066_dmc_ddrconf_table[] = {
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/*
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* [5:4] row(13+n)
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* [1:0] col(9+n), assume bw=2
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* row col,bw
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*/
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0,
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(2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
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(1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
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(0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
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(2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
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(1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
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(0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
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(1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
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(0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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};
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#define TEST_PATTERN 0x5aa5f00f
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#define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4)
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#define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5)
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static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n)
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{
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int i;
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for (i = 0; i < n / sizeof(u32); i++) {
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writel(*src, dest);
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src++;
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dest++;
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}
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}
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static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
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{
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u32 phy_ctl_srstn_shift = 13;
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u32 ctl_psrstn_shift = 11;
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u32 ctl_srstn_shift = 10;
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u32 phy_psrstn_shift = 9;
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u32 phy_srstn_shift = 8;
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rk_clrsetreg(&cru->cru_softrst_con[5],
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1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
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1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
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1 << phy_srstn_shift,
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phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
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ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
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phy << phy_srstn_shift);
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}
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static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
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{
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u32 phy_ctl_srstn_shift = 13;
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rk_clrsetreg(&cru->cru_softrst_con[5],
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1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
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}
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static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru,
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struct rk3288_ddr_publ *publ,
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int channel)
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{
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int i;
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rk3066_dmc_ddr_reset(cru, channel, 1, 1);
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udelay(1);
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clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
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for (i = 0; i < 4; i++)
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clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
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udelay(10);
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setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
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for (i = 0; i < 4; i++)
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setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
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udelay(10);
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rk3066_dmc_ddr_reset(cru, channel, 1, 0);
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udelay(10);
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rk3066_dmc_ddr_reset(cru, channel, 0, 0);
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udelay(10);
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}
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static void rk3066_dmc_phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq)
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{
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int i;
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if (freq <= 250000000) {
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if (freq <= 150000000)
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clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
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else
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setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
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setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
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for (i = 0; i < 4; i++)
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setbits_le32(&publ->datx8[i].dxdllcr,
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DXDLLCR_DLLDIS);
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setbits_le32(&publ->pir, PIR_DLLBYP);
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} else {
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clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
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clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
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for (i = 0; i < 4; i++) {
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clrbits_le32(&publ->datx8[i].dxdllcr,
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DXDLLCR_DLLDIS);
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}
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clrbits_le32(&publ->pir, PIR_DLLBYP);
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}
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}
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static void rk3066_dmc_dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
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{
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writel(DFI_INIT_START, &pctl->dfistcfg0);
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writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
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&pctl->dfistcfg1);
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writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
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writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
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&pctl->dfilpcfg0);
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writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
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writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
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writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
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writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
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writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
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writel(1, &pctl->dfitphyupdtype0);
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/* CS0 and CS1 write ODT enable. */
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writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
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&pctl->dfiodtcfg);
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/* Write ODT length. */
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writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
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/* Disable phyupd and ctrlupd. */
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writel(0, &pctl->dfiupdcfg);
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}
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static void rk3066_dmc_ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel,
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bool ddr3_mode)
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{
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uint mask, val;
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mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
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val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
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rk_clrsetreg(&grf->soc_con2, mask, val);
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}
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static void rk3066_dmc_ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable)
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{
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uint mask, val;
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mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
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val = enable << RANK_TO_ROW15_EN_SHIFT;
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rk_clrsetreg(&grf->soc_con2, mask, val);
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}
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static void rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
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struct rk3066_dmc_sdram_params *sdram_params,
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struct rk3066_grf *grf)
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{
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rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
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sizeof(sdram_params->pctl_timing));
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switch (sdram_params->base.dramtype) {
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case DDR3:
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if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
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writel(sdram_params->pctl_timing.tcl - 3,
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&pctl->dfitrddataen);
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} else {
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writel(sdram_params->pctl_timing.tcl - 2,
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&pctl->dfitrddataen);
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}
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writel(sdram_params->pctl_timing.tcwl - 1,
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&pctl->dfitphywrlat);
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writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
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DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
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1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
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&pctl->mcfg);
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rk3066_dmc_ddr_set_ddr3_mode(grf, channel, true);
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break;
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}
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setbits_le32(&pctl->scfg, 1);
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}
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static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel,
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struct rk3066_dmc_sdram_params *sdram_params)
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{
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struct rk3288_ddr_publ *publ = chan->publ;
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struct rk3188_msch *msch = chan->msch;
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uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
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u32 dinit2;
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int i;
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dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
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/* Set DDR PHY timing. */
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rk3066_dmc_copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
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sizeof(sdram_params->phy_timing));
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writel(sdram_params->base.noc_timing, &msch->ddrtiming);
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writel(0x3f, &msch->readlatency);
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writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
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DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
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8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
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writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
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DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
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&publ->ptr[1]);
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writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
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DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
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&publ->ptr[2]);
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switch (sdram_params->base.dramtype) {
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case DDR3:
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clrbits_le32(&publ->pgcr, 0x1f);
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clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
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DDRMD_DDR3 << DDRMD_SHIFT);
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break;
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}
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if (sdram_params->base.odt) {
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/* Enable dynamic RTT. */
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for (i = 0; i < 4; i++)
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setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
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} else {
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/* Disable dynamic RTT. */
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for (i = 0; i < 4; i++)
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clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
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}
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}
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static void rk3066_dmc_phy_init(struct rk3288_ddr_publ *publ)
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{
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setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
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| PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
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udelay(1);
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while ((readl(&publ->pgsr) &
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(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
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(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
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;
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}
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static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
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u32 cmd, u32 arg)
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{
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writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
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udelay(1);
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while (readl(&pctl->mcmd) & START_CMD)
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;
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}
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static inline void rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl,
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u32 rank, u32 cmd, u32 ma, u32 op)
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{
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rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
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(op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
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}
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static void rk3066_dmc_memory_init(struct rk3288_ddr_publ *publ,
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u32 dramtype)
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{
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setbits_le32(&publ->pir,
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(PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
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| PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
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| (dramtype == DDR3 ? PIR_DRAMRST : 0)));
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udelay(1);
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while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
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!= (PGSR_IDONE | PGSR_DLDONE))
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;
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}
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static void rk3066_dmc_move_to_config_state(struct rk3288_ddr_publ *publ,
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struct rk3288_ddr_pctl *pctl)
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{
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unsigned int state;
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while (1) {
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state = readl(&pctl->stat) & PCTL_STAT_MSK;
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switch (state) {
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case LOW_POWER:
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writel(WAKEUP_STATE, &pctl->sctl);
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while ((readl(&pctl->stat) & PCTL_STAT_MSK)
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!= ACCESS)
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;
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/* Wait DLL lock. */
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while ((readl(&publ->pgsr) & PGSR_DLDONE)
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!= PGSR_DLDONE)
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;
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/*
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* If at low power state we need to wakeup first
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* and then enter the config.
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*/
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fallthrough;
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case ACCESS:
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fallthrough;
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case INIT_MEM:
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writel(CFG_STATE, &pctl->sctl);
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while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
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;
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break;
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case CONFIG:
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return;
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default:
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break;
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}
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}
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}
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static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel,
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u32 n, struct rk3066_grf *grf)
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{
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struct rk3288_ddr_pctl *pctl = chan->pctl;
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struct rk3288_ddr_publ *publ = chan->publ;
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struct rk3188_msch *msch = chan->msch;
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if (n == 1) {
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setbits_le32(&pctl->ppcfg, 1);
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setbits_le32(&msch->ddrtiming, 1 << 31);
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/* Data byte disable. */
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clrbits_le32(&publ->datx8[2].dxgcr, 1);
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clrbits_le32(&publ->datx8[3].dxgcr, 1);
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/* Disable DLL. */
|
||||
setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
|
||||
setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
|
||||
} else {
|
||||
clrbits_le32(&pctl->ppcfg, 1);
|
||||
clrbits_le32(&msch->ddrtiming, 1 << 31);
|
||||
/* Data byte enable.*/
|
||||
setbits_le32(&publ->datx8[2].dxgcr, 1);
|
||||
setbits_le32(&publ->datx8[3].dxgcr, 1);
|
||||
|
||||
/* Enable DLL. */
|
||||
clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
|
||||
clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
|
||||
/* Reset DLL. */
|
||||
clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
|
||||
clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
|
||||
udelay(10);
|
||||
setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
|
||||
setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
|
||||
}
|
||||
setbits_le32(&pctl->dfistcfg0, 1 << 2);
|
||||
}
|
||||
|
||||
static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel,
|
||||
struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
unsigned int j;
|
||||
int ret = 0;
|
||||
u32 rank;
|
||||
int i;
|
||||
u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
|
||||
struct rk3288_ddr_publ *publ = chan->publ;
|
||||
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
||||
|
||||
/* Disable auto refresh. */
|
||||
writel(0, &pctl->trefi);
|
||||
|
||||
if (sdram_params->base.dramtype != LPDDR3)
|
||||
setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
|
||||
rank = sdram_params->ch[channel].rank | 1;
|
||||
for (j = 0; j < ARRAY_SIZE(step); j++) {
|
||||
/*
|
||||
* Trigger QSTRN and RVTRN.
|
||||
* Clear DTDONE status.
|
||||
*/
|
||||
setbits_le32(&publ->pir, PIR_CLRSR);
|
||||
|
||||
/* Trigger DTT. */
|
||||
setbits_le32(&publ->pir,
|
||||
PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
|
||||
PIR_CLRSR);
|
||||
udelay(1);
|
||||
/* Wait echo byte DTDONE. */
|
||||
while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
|
||||
!= rank)
|
||||
;
|
||||
while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
|
||||
!= rank)
|
||||
;
|
||||
if (!(readl(&pctl->ppcfg) & 1)) {
|
||||
while ((readl(&publ->datx8[2].dxgsr[0])
|
||||
& rank) != rank)
|
||||
;
|
||||
while ((readl(&publ->datx8[3].dxgsr[0])
|
||||
& rank) != rank)
|
||||
;
|
||||
}
|
||||
if (readl(&publ->pgsr) &
|
||||
(PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Send some auto refresh to complement the lost while DTT. */
|
||||
for (i = 0; i < (rank > 1 ? 8 : 4); i++)
|
||||
rk3066_dmc_send_command(pctl, rank, REF_CMD, 0);
|
||||
|
||||
if (sdram_params->base.dramtype != LPDDR3)
|
||||
clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
|
||||
|
||||
/* Resume auto refresh. */
|
||||
writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan)
|
||||
{
|
||||
struct rk3288_ddr_publ *publ = chan->publ;
|
||||
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
||||
unsigned int state;
|
||||
|
||||
while (1) {
|
||||
state = readl(&pctl->stat) & PCTL_STAT_MSK;
|
||||
|
||||
switch (state) {
|
||||
case LOW_POWER:
|
||||
if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
|
||||
LP_TRIG_MASK) == 1)
|
||||
return;
|
||||
|
||||
writel(WAKEUP_STATE, &pctl->sctl);
|
||||
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
|
||||
;
|
||||
/* Wait DLL lock. */
|
||||
while ((readl(&publ->pgsr) & PGSR_DLDONE)
|
||||
!= PGSR_DLDONE)
|
||||
;
|
||||
break;
|
||||
case INIT_MEM:
|
||||
writel(CFG_STATE, &pctl->sctl);
|
||||
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
|
||||
;
|
||||
fallthrough;
|
||||
case CONFIG:
|
||||
writel(GO_STATE, &pctl->sctl);
|
||||
while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
|
||||
;
|
||||
break;
|
||||
case ACCESS:
|
||||
return;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum,
|
||||
struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
struct rk3288_ddr_publ *publ = chan->publ;
|
||||
|
||||
if (sdram_params->ch[chnum].bk == 3)
|
||||
clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
|
||||
1 << PDQ_SHIFT);
|
||||
else
|
||||
clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
|
||||
|
||||
writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
|
||||
}
|
||||
|
||||
static void rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram,
|
||||
struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
unsigned int chan;
|
||||
u32 sys_reg = 0;
|
||||
|
||||
sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
|
||||
sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
|
||||
for (chan = 0; chan < sdram_params->num_channels; chan++) {
|
||||
const struct rk3288_sdram_channel *info =
|
||||
&sdram_params->ch[chan];
|
||||
|
||||
sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
|
||||
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
|
||||
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
|
||||
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
|
||||
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
|
||||
sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
|
||||
sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
|
||||
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
|
||||
sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
|
||||
|
||||
rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
|
||||
}
|
||||
if (sdram_params->ch[0].rank == 2)
|
||||
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0);
|
||||
else
|
||||
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1);
|
||||
|
||||
writel(sys_reg, &dram->pmu->sys_reg[2]);
|
||||
}
|
||||
|
||||
static int rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel,
|
||||
struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
int reg;
|
||||
int need_trainig = 0;
|
||||
const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
|
||||
struct rk3288_ddr_publ *publ = chan->publ;
|
||||
|
||||
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0);
|
||||
|
||||
if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) {
|
||||
debug("first data training fail!\n");
|
||||
reg = readl(&publ->datx8[0].dxgsr[0]);
|
||||
/* Check the result for rank 0. */
|
||||
if (channel == 0 && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
|
||||
debug("data training fail!\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Check the result for rank 1. */
|
||||
if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
|
||||
sdram_params->ch[channel].rank = 1;
|
||||
clrsetbits_le32(&publ->pgcr, 0xF << 18,
|
||||
sdram_params->ch[channel].rank << 18);
|
||||
need_trainig = 1;
|
||||
}
|
||||
reg = readl(&publ->datx8[2].dxgsr[0]);
|
||||
if (reg & (1 << 4)) {
|
||||
sdram_params->ch[channel].bw = 1;
|
||||
rk3066_dmc_set_bandwidth_ratio(chan, channel,
|
||||
sdram_params->ch[channel].bw,
|
||||
dram->grf);
|
||||
need_trainig = 1;
|
||||
}
|
||||
}
|
||||
/* Assume that the die bit width is equel to the chip bit width. */
|
||||
sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
|
||||
|
||||
if (need_trainig &&
|
||||
(rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) {
|
||||
if (sdram_params->base.dramtype == LPDDR3) {
|
||||
rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 1);
|
||||
udelay(10);
|
||||
rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 0);
|
||||
udelay(10);
|
||||
}
|
||||
debug("2nd data training failed!");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel,
|
||||
struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
int row, col;
|
||||
unsigned int addr;
|
||||
const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
|
||||
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
||||
struct rk3288_ddr_publ *publ = chan->publ;
|
||||
int ret = 0;
|
||||
|
||||
/* Detect col. */
|
||||
for (col = 11; col >= 9; col--) {
|
||||
writel(0, CONFIG_SYS_SDRAM_BASE);
|
||||
addr = CONFIG_SYS_SDRAM_BASE +
|
||||
(1 << (col + sdram_params->ch[channel].bw - 1));
|
||||
writel(TEST_PATTERN, addr);
|
||||
if ((readl(addr) == TEST_PATTERN) &&
|
||||
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
|
||||
break;
|
||||
}
|
||||
if (col == 8) {
|
||||
debug("Col detect error\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
} else {
|
||||
sdram_params->ch[channel].col = col;
|
||||
}
|
||||
|
||||
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1);
|
||||
rk3066_dmc_move_to_config_state(publ, pctl);
|
||||
writel(1, &chan->msch->ddrconf);
|
||||
rk3066_dmc_move_to_access_state(chan);
|
||||
/* Detect row, max 15, min13 for rk3066 */
|
||||
for (row = 16; row >= 13; row--) {
|
||||
writel(0, CONFIG_SYS_SDRAM_BASE);
|
||||
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
|
||||
writel(TEST_PATTERN, addr);
|
||||
if ((readl(addr) == TEST_PATTERN) &&
|
||||
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
|
||||
break;
|
||||
}
|
||||
if (row == 12) {
|
||||
debug("Row detect error\n");
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
sdram_params->ch[channel].cs1_row = row;
|
||||
sdram_params->ch[channel].row_3_4 = 0;
|
||||
debug("chn %d col %d, row %d\n", channel, col, row);
|
||||
sdram_params->ch[channel].cs0_row = row;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
int i, tmp, size, ret = 0;
|
||||
|
||||
tmp = sdram_params->ch[0].col - 9;
|
||||
tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
|
||||
tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
|
||||
size = ARRAY_SIZE(rk3066_dmc_ddrconf_table) / sizeof(rk3066_dmc_ddrconf_table[0]);
|
||||
for (i = 0; i < size; i++)
|
||||
if (tmp == rk3066_dmc_ddrconf_table[i])
|
||||
break;
|
||||
if (i >= size) {
|
||||
debug("niu config not found\n");
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
debug("niu config %d\n", i);
|
||||
sdram_params->base.ddrconfig = i;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram,
|
||||
struct rk3066_dmc_sdram_params *sdram_params)
|
||||
{
|
||||
int channel;
|
||||
int zqcr;
|
||||
int ret;
|
||||
|
||||
if ((sdram_params->base.dramtype == DDR3 &&
|
||||
sdram_params->base.ddr_freq > 800000000)) {
|
||||
debug("SDRAM frequency is too high!");
|
||||
return -E2BIG;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
|
||||
if (ret) {
|
||||
debug("Could not set DDR clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (channel = 0; channel < 1; channel++) {
|
||||
const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
|
||||
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
||||
struct rk3288_ddr_publ *publ = chan->publ;
|
||||
|
||||
rk3066_dmc_phy_pctrl_reset(dram->cru, publ, channel);
|
||||
rk3066_dmc_phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
|
||||
|
||||
rk3066_dmc_dfi_cfg(pctl, sdram_params->base.dramtype);
|
||||
|
||||
rk3066_dmc_pctl_cfg(channel, pctl, sdram_params, dram->grf);
|
||||
|
||||
rk3066_dmc_phy_cfg(chan, channel, sdram_params);
|
||||
|
||||
rk3066_dmc_phy_init(publ);
|
||||
|
||||
writel(POWER_UP_START, &pctl->powctl);
|
||||
while (!(readl(&pctl->powstat) & POWER_UP_DONE))
|
||||
;
|
||||
|
||||
rk3066_dmc_memory_init(publ, sdram_params->base.dramtype);
|
||||
rk3066_dmc_move_to_config_state(publ, pctl);
|
||||
|
||||
/* Use 32bit bus width for detection. */
|
||||
sdram_params->ch[channel].bw = 2;
|
||||
rk3066_dmc_set_bandwidth_ratio(chan, channel,
|
||||
sdram_params->ch[channel].bw, dram->grf);
|
||||
/*
|
||||
* set cs, using n=3 for detect
|
||||
* CS0, n=1
|
||||
* CS1, n=2
|
||||
* CS0 & CS1, n = 3
|
||||
*/
|
||||
sdram_params->ch[channel].rank = 2;
|
||||
clrsetbits_le32(&publ->pgcr, 0xF << 18,
|
||||
(sdram_params->ch[channel].rank | 1) << 18);
|
||||
|
||||
/* DS=40ohm,ODT=155ohm */
|
||||
zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
|
||||
2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
|
||||
0x19 << PD_OUTPUT_SHIFT;
|
||||
writel(zqcr, &publ->zq1cr[0]);
|
||||
writel(zqcr, &publ->zq0cr[0]);
|
||||
|
||||
/* Detect the rank and bit-width with data-training. */
|
||||
writel(1, &chan->msch->ddrconf);
|
||||
rk3066_dmc_sdram_rank_bw_detect(dram, channel, sdram_params);
|
||||
|
||||
if (sdram_params->base.dramtype == LPDDR3) {
|
||||
u32 i;
|
||||
|
||||
writel(0, &pctl->mrrcfg0);
|
||||
|
||||
for (i = 0; i < 17; i++)
|
||||
rk3066_dmc_send_command_op(pctl, 1, MRR_CMD, i, 0);
|
||||
}
|
||||
writel(4, &chan->msch->ddrconf);
|
||||
rk3066_dmc_move_to_access_state(chan);
|
||||
/* DDR3 and LPDDR3 are always 8 bank, no need to detect. */
|
||||
sdram_params->ch[channel].bk = 3;
|
||||
/* Detect Col and Row number. */
|
||||
ret = rk3066_dmc_sdram_col_row_detect(dram, channel, sdram_params);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
/* Find NIU DDR configuration. */
|
||||
ret = rk3066_dmc_sdram_get_niu_config(sdram_params);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
rk3066_dmc_dram_all_config(dram, sdram_params);
|
||||
debug("SDRAM init OK!\n");
|
||||
|
||||
return 0;
|
||||
error:
|
||||
debug("SDRAM init failed!\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
static int rk3066_dmc_setup_sdram(struct udevice *dev)
|
||||
{
|
||||
struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
|
||||
struct rk3066_dmc_sdram_params *params = dev_get_plat(dev);
|
||||
|
||||
return rk3066_dmc_sdram_init(priv, params);
|
||||
}
|
||||
|
||||
static int rk3066_dmc_conv_of_plat(struct udevice *dev)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev);
|
||||
struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat;
|
||||
int ret;
|
||||
|
||||
memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
|
||||
sizeof(plat->pctl_timing));
|
||||
memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
|
||||
sizeof(plat->phy_timing));
|
||||
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
|
||||
/* RK3066 supports dual-channel, set default channel num to 2. */
|
||||
plat->num_channels = 1;
|
||||
ret = regmap_init_mem_plat(dev, of_plat->reg,
|
||||
ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
#else
|
||||
return -EINVAL;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int rk3066_dmc_probe(struct udevice *dev)
|
||||
{
|
||||
struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
|
||||
|
||||
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
|
||||
|
||||
if (IS_ENABLED(CONFIG_TPL_BUILD)) {
|
||||
struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev);
|
||||
struct regmap *map;
|
||||
struct udevice *dev_clk;
|
||||
int ret;
|
||||
|
||||
ret = rk3066_dmc_conv_of_plat(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
|
||||
if (IS_ERR(map))
|
||||
return PTR_ERR(map);
|
||||
priv->chan[0].msch = regmap_get_range(map, 0);
|
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
|
||||
priv->chan[0].pctl = regmap_get_range(plat->map, 0);
|
||||
priv->chan[0].publ = regmap_get_range(plat->map, 1);
|
||||
|
||||
ret = rockchip_get_clk(&dev_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->ddr_clk.id = CLK_DDR;
|
||||
ret = clk_request(dev_clk, &priv->ddr_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->cru = rockchip_get_cru();
|
||||
if (IS_ERR(priv->cru))
|
||||
return PTR_ERR(priv->cru);
|
||||
|
||||
ret = rk3066_dmc_setup_sdram(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
priv->info.base = CONFIG_SYS_SDRAM_BASE;
|
||||
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info)
|
||||
{
|
||||
struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
|
||||
|
||||
*info = priv->info;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ram_ops rk3066_dmc_ops = {
|
||||
.get_info = rk3066_dmc_get_info,
|
||||
};
|
||||
|
||||
static const struct udevice_id rk3066_dmc_ids[] = {
|
||||
{ .compatible = "rockchip,rk3066-dmc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3066_dmc) = {
|
||||
.name = "rockchip_rk3066_dmc",
|
||||
.id = UCLASS_RAM,
|
||||
.ops = &rk3066_dmc_ops,
|
||||
.probe = rk3066_dmc_probe,
|
||||
.of_match = rk3066_dmc_ids,
|
||||
.priv_auto = sizeof(struct rk3066_dmc_dram_info),
|
||||
#if IS_ENABLED(CONFIG_TPL_BUILD)
|
||||
.plat_auto = sizeof(struct rk3066_dmc_sdram_params),
|
||||
#endif
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user