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arm: socfpga: mcvevk: Update DRAM clock to 400MHz

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The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed
to 400MHz to make use of these DRAMs completely.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-09-08 19:51:05 +02:00
parent 89983478bd
commit 4ae6cfe332
3 changed files with 85 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

128
board/denx/mcvevk/qts/iocsr_config.h
View File

@ -130,7 +130,7 @@ const unsigned long iocsr_scan_chain2_table[] = {
};
const unsigned long iocsr_scan_chain3_table[] = {
0x0CC20D80,
0x0C420D80,
0x0C3000FF,
0x0A804001,
0x07900000,
@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00001000,
0xA0000034,
0x0D000001,
0xC0680618,
0x45034071,
0x1A681A01,
0x806180D0,
0x34071C06,
0x01A034D0,
0x380D0000,
0x0820680E,
0x034D0340,
0xC0680A28,
0x45034030,
0x12481A01,
0x80A280D0,
0x34030C06,
0x01A01450,
0x280D0000,
0x30C0680A,
0x02490340,
0xD000001A,
0x0680E380,
0x0680A280,
0x10040000,
0x00200000,
0x10040000,
@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00001000,
0xA0000034,
0x0D000001,
0xC0680618,
0x45034071,
0x1A681A01,
0x80E380D0,
0x34071C06,
0xC0680A28,
0x49034030,
0x12481A02,
0x80A280D0,
0x34030C06,
0x01A00040,
0x380D0002,
0x71C0680E,
0x034D0340,
0xD01A681A,
0x06806180,
0x280D0002,
0x30C0680A,
0x02490340,
0xD00A281A,
0x0680A280,
0x10040000,
0x00200000,
0x10040000,
@ -285,7 +285,7 @@ const unsigned long iocsr_scan_chain3_table[] = {
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x01C3A890,
0xAA0D4000,
0x01C3A800,
0x00040100,
@ -313,7 +313,7 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x0070EA24,
0x2A835000,
0x0070EA00,
0x00010040,
@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D,
0x1A041414,
0x00D00000,
0x04864000,
0x69A47A01,
0x932CA3DA,
0xF459651E,
0x03549248,
0x18864000,
0x49247A06,
0x9A28A3D7,
0xF511451E,
0x0356E388,
0x821A0000,
0x0000D000,
0x030C0680,
0xDA69A47A,
0x1E9228A3,
0x48F45965,
0x000354D3,
0x05140680,
0xD749247A,
0x1E9A28A3,
0x88F51145,
0x00034EE3,
0x00080000,
0x00001000,
0x00080200,
@ -359,7 +359,7 @@ const unsigned long iocsr_scan_chain3_table[] = {
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x01C3A890,
0xAA0D4000,
0x01C3A800,
0x00040000,
@ -387,7 +387,7 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x2A835000,
0x0070EA00,
0x2A835000,
0x0070EA00,
0x0070EA24,
0x2A835000,
0x0070EA00,
0x00015000,
@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xE228A3D6,
0xF459651E,
0x034CD348,
0x821A0041,
0x18864000,
0x49247A06,
0xEBCF23D7,
0xF611451E,
0x034E9248,
0x821A038E,
0x0000D000,
0x00000680,
0xD669A47A,
0x1E9228A3,
0x48F45965,
0x00034492,
0xD749247A,
0x1E9BCF23,
0x88F61145,
0x00034EE3,
0x00080000,
0x00001000,
0x00080000,
@ -433,7 +433,7 @@ const unsigned long iocsr_scan_chain3_table[] = {
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
0x01C3A800,
0x01C3A890,
0xAA0D4000,
0x01C3A800,
0x00040000,
@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0x9228A3D6,
0xF459651E,
0x034CD348,
0x18864000,
0x49247A06,
0x9A28A3D7,
0xF431451E,
0x034E9248,
0x821A0000,
0x0000D000,
0x00000680,
0xD659647A,
0x1E932CA3,
0x48F65965,
0x00034CD3,
0xD749247A,
0x1E9A28A3,
0x88F61145,
0x000356E3,
0x00080000,
0x00001000,
0x00080000,
@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F1690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0x932CA3D6,
0xF659651E,
0x034CD348,
0x08864000,
0x49247A02,
0xEBCF23DB,
0xF431451E,
0x0356E388,
0x821A0000,
0x0000D000,
0x00000680,
0xD669A47A,
0x1E9228A3,
0x48F45965,
0x00034CD3,
0xD749247A,
0x1EEBCF23,
0x88F43E79,
0x000356A2,
0x00080000,
0x00001000,
0x00080000,

6
board/denx/mcvevk/qts/pll_config.h
View File

@ -45,8 +45,8 @@
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
@ -63,7 +63,7 @@
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000

36
board/denx/mcvevk/qts/sdram_config.h
View File

@ -34,19 +34,19 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
@ -132,7 +132,7 @@
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
#define IO_DELAY_PER_OPA_TAP 375
#define IO_DELAY_PER_OPA_TAP 312
#define IO_DLL_CHAIN_LENGTH 8
#define IO_DQDQS_OUT_PHASE_MAX 0
#define IO_DQS_EN_DELAY_MAX 31
@ -147,7 +147,7 @@
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32
@ -160,10 +160,10 @@
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
#define TINIT_CNTR0_VAL 82
#define TINIT_CNTR0_VAL 99
#define TINIT_CNTR1_VAL 32
#define TINIT_CNTR2_VAL 32
#define TRESET_CNTR0_VAL 82
#define TRESET_CNTR0_VAL 99
#define TRESET_CNTR1_VAL 99
#define TRESET_CNTR2_VAL 10
@ -171,14 +171,14 @@
const u32 ac_rom_init[] = {
0x20700000,
0x20780000,
0x10080221,
0x10080320,
0x10080421,
0x10080520,
0x10090044,
0x100a0008,
0x100b0000,
0x10380400,
0x10080241,
0x100802c0,
0x10080441,
0x100804c0,
0x100a0024,
0x10090010,
0x100b0000,