spi: Zap andes_spi driver
Zap andes_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Macpaul Lin <macpaul@andestech.com>
This commit is contained in:
Jagan Teki
parent
9c5a70dbe8
commit
4ad479e3d6
@ -17,7 +17,6 @@ endif
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obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
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obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
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obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
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obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
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obj-$(CONFIG_ANDES_SPI) += andes_spi.o
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obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
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obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
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obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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@ -1,284 +0,0 @@
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/*
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* Driver of Andes SPI Controller
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*
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* (C) Copyright 2011 Andes Technology
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* Macpaul Lin <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include "andes_spi.h"
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void spi_init(void)
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{
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/* do nothing */
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}
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static void andes_spi_spit_en(struct andes_spi_slave *ds)
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{
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unsigned int dcr = readl(&ds->regs->dcr);
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debug("%s: dcr: %x, write value: %x\n",
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__func__, dcr, (dcr | ANDES_SPI_DCR_SPIT));
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writel((dcr | ANDES_SPI_DCR_SPIT), &ds->regs->dcr);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct andes_spi_slave *ds;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ds = spi_alloc_slave(struct andes_spi_slave, bus, cs);
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if (!ds)
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return NULL;
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ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
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/*
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* The hardware of andes_spi will set its frequency according
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* to APB/AHB bus clock. Hence the hardware doesn't allow changing of
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* requency and so the user requested speed is always ignored.
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*/
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ds->freq = max_hz;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct andes_spi_slave *ds = to_andes_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct andes_spi_slave *ds = to_andes_spi(slave);
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unsigned int apb;
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unsigned int baud;
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/* Enable the SPI hardware */
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writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
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udelay(1000);
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/* setup format */
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baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) & 0xFF;
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/*
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* SPI_CLK = AHB bus clock / ((BAUD + 1)*2)
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* BAUD = AHB bus clock / SPI_CLK / 2) - 1
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*/
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apb = (readl(&ds->regs->apb) & 0xffffff00) | baud;
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writel(apb, &ds->regs->apb);
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/* no interrupts */
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writel(0, &ds->regs->ie);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct andes_spi_slave *ds = to_andes_spi(slave);
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/* Disable the SPI hardware */
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writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
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}
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static int andes_spi_read(struct spi_slave *slave, unsigned int len,
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u8 *rxp, unsigned long flags)
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{
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struct andes_spi_slave *ds = to_andes_spi(slave);
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unsigned int i, left;
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unsigned int data;
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debug("%s: slave: %x, len: %d, rxp: %x, flags: %d\n",
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__func__, slave, len, rxp, flags);
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debug("%s: data: ", __func__);
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while (len > 0) {
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left = min(len, 4);
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data = readl(&ds->regs->data);
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debug(" ");
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for (i = 0; i < left; i++) {
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debug("%02x ", data & 0xff);
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*rxp++ = data;
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data >>= 8;
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len--;
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}
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}
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debug("\n");
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return 0;
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}
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static int andes_spi_write(struct spi_slave *slave, unsigned int wlen,
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unsigned int rlen, const u8 *txp, unsigned long flags)
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{
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struct andes_spi_slave *ds = to_andes_spi(slave);
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unsigned int data;
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unsigned int i, left;
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unsigned int spit_enabled = 0;
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debug("%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n",
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__func__, slave, wlen, rlen, txp, flags);
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/* The value of wlen and rlen wrote to register must minus 1 */
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if (rlen == 0) /* write only */
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writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) |
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ANDES_SPI_DCR_RCNT(0), &ds->regs->dcr);
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else /* write then read */
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writel(ANDES_SPI_DCR_MODE_WR | ANDES_SPI_DCR_WCNT(wlen-1) |
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ANDES_SPI_DCR_RCNT(rlen-1), &ds->regs->dcr);
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/* wait till SPIBSY is cleared */
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while (readl(&ds->regs->st) & ANDES_SPI_ST_SPIBSY)
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;
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/* data write process */
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debug("%s: txp: ", __func__);
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while (wlen > 0) {
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/* clear the data */
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data = 0;
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/* data are usually be read 32bits once a time */
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left = min(wlen, 4);
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for (i = 0; i < left; i++) {
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debug("%x ", *txp);
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data |= *txp++ << (i * 8);
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wlen--;
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}
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debug("\n");
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debug("data: %08x\n", data);
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debug("streg before write: %08x\n", readl(&ds->regs->st));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->st) & ANDES_SPI_ST_TXFEL)
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;
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writel(data, &ds->regs->data);
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debug("streg after write: %08x\n", readl(&ds->regs->st));
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if (spit_enabled == 0) {
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/* enable SPIT bit - trigger the tx and rx progress */
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andes_spi_spit_en(ds);
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spit_enabled = 1;
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}
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}
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debug("\n");
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return 0;
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}
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/*
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* spi_xfer:
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* Since andes_spi doesn't support independent command transaction,
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* that is, write and than read must be operated in continuous
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* execution, there is no need to set dcr and trigger spit again in
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* RX process.
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*/
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int len;
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static int op_nextime;
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static u8 tmp_cmd[5];
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static int tmp_wlen;
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unsigned int i;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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debug("%s: slave: %08x, bitlen: %d, dout: "
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"%08x, din: %08x, flags: %d, len: %d\n",
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__func__, slave, bitlen, dout, din, flags, len);
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/*
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* Important:
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* andes_spi's hardware doesn't support 2 data channel. The read
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* and write cmd/data share the same register (data register).
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*
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* If a command has write and read transaction, you cannot do write
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* this time and then do read on next time.
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*
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* A command writes first with a read response must indicating
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* the read length in write operation. Hence the write action must
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* be stored temporary and wait until the next read action has been
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* arrived. Then we flush the write and read action out together.
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*/
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if (!dout) {
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if (op_nextime == 1) {
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/* flags should be SPI_XFER_END, value is 2 */
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op_nextime = 0;
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andes_spi_write(slave, tmp_wlen, len, tmp_cmd, flags);
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}
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return andes_spi_read(slave, len, din, flags);
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} else if (!din) {
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if (flags == SPI_XFER_BEGIN) {
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/* store the write command and do operation next time */
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op_nextime = 1;
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memset(tmp_cmd, 0, sizeof(tmp_cmd));
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memcpy(tmp_cmd, dout, len);
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debug("%s: tmp_cmd: ", __func__);
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for (i = 0; i < len; i++)
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debug("%x ", *(tmp_cmd + i));
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debug("\n");
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tmp_wlen = len;
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} else {
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/*
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* flags should be (SPI_XFER_BEGIN | SPI_XFER_END),
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* the value is 3.
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*/
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if (op_nextime == 1) {
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/* flags should be SPI_XFER_END, value is 2 */
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op_nextime = 0;
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/* flags 3 implies write only */
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andes_spi_write(slave, tmp_wlen, 0, tmp_cmd, 3);
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}
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debug("flags: %x\n", flags);
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return andes_spi_write(slave, len, 0, dout, flags);
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}
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}
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out:
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return 0;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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@ -1,115 +0,0 @@
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/*
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* Register definitions for the Andes SPI Controller
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*
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* (C) Copyright 2011 Andes Technology
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* Macpaul Lin <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ANDES_SPI_H
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#define __ANDES_SPI_H
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struct andes_spi_regs {
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unsigned int apb; /* 0x00 - APB SPI interface setting */
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unsigned int pio; /* 0x04 - PIO reg */
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unsigned int cr; /* 0x08 - SPI Control reg */
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unsigned int st; /* 0x0c - SPI Status reg */
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unsigned int ie; /* 0x10 - Interrupt Enable reg */
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unsigned int ist; /* 0x14 - Interrupt Status reg */
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unsigned int dcr; /* 0x18 - data control reg */
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unsigned int data; /* 0x1c - data register */
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unsigned int ahb; /* 0x20 - AHB SPI interface setting */
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unsigned int ver; /* 0x3c - SPI version reg */
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};
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#define BIT(x) (1 << (x))
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/* 0x00 - APB SPI interface setting register */
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#define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0)
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#define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16)
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#define ANDES_SPI_APB_SPNTS BIT(20) /* 0: normal, 1: delay */
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#define ANDES_SPI_APB_CPHA BIT(24) /* 0: Sampling at odd edges */
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#define ANDES_SPI_APB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
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#define ANDES_SPI_APB_MSSL BIT(26) /* 0: SPI Master, 1: slave */
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/* 0x04 - PIO register */
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#define ANDES_SPI_PIO_MISO BIT(0) /* input value of pin MISO */
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#define ANDES_SPI_PIO_MOSI BIT(1) /* I/O value of pin MOSI */
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#define ANDES_SPI_PIO_SCK BIT(2) /* I/O value of pin SCK */
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#define ANDES_SPI_PIO_CS BIT(3) /* I/O value of pin CS */
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#define ANDES_SPI_PIO_PIOE BIT(4) /* Programming IO Enable */
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/* 0x08 - SPI Control register */
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#define ANDES_SPI_CR_SPIRST BIT(0) /* SPI mode reset */
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#define ANDES_SPI_CR_RXFRST BIT(1) /* RxFIFO reset */
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#define ANDES_SPI_CR_TXFRST BIT(2) /* TxFIFO reset */
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#define ANDES_SPI_CR_RXFTH(x) (((x) & 0x1f) << 10) /* RxFIFO Threshold */
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#define ANDES_SPI_CR_TXFTH(x) (((x) & 0x1f) << 18) /* TxFIFO Threshold */
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/* 0x0c - SPI Status register */
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#define ANDES_SPI_ST_SPIBSY BIT(0) /* SPI Transfer is active */
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#define ANDES_SPI_ST_RXFEM BIT(8) /* RxFIFO Empty Flag */
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#define ANDES_SPI_ST_RXFEL BIT(9) /* RxFIFO Full Flag */
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#define ANDES_SPI_ST_RXFVE(x) (((x) >> 10) & 0x1f)
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#define ANDES_SPI_ST_TXFEM BIT(16) /* TxFIFO Empty Flag */
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#define ANDES_SPI_ST_TXFEL BIT(7) /* TxFIFO Full Flag */
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#define ANDES_SPI_ST_TXFVE(x) (((x) >> 18) & 0x1f)
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/* 0x10 - Interrupt Enable register */
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#define ANDES_SPI_IE_RXFORIE BIT(0) /* RxFIFO overrun intr */
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#define ANDES_SPI_IE_TXFURIE BIT(1) /* TxFOFO underrun intr */
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#define ANDES_SPI_IE_RXFTHIE BIT(2) /* RxFIFO threshold intr */
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#define ANDES_SPI_IE_TXFTHIE BIT(3) /* TxFIFO threshold intr */
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#define ANDES_SPI_IE_SPIEIE BIT(4) /* SPI transmit END intr */
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#define ANDES_SPI_IE_SPCFIE BIT(5) /* AHB/APB TxReq conflict */
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/* 0x14 - Interrupt Status Register */
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#define ANDES_SPI_IST_RXFORI BIT(0) /* has RxFIFO overrun */
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#define ANDES_SPI_IST_TXFURI BIT(1) /* has TxFOFO underrun */
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#define ANDES_SPI_IST_RXFTHI BIT(2) /* has RxFIFO threshold */
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#define ANDES_SPI_IST_TXFTHI BIT(3) /* has TxFIFO threshold */
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#define ANDES_SPI_IST_SPIEI BIT(4) /* has SPI transmit END */
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#define ANDES_SPI_IST_SPCFI BIT(5) /* has AHB/APB TxReq conflict */
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/* 0x18 - Data Control Register */
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#define ANDES_SPI_DCR_RCNT(x) (((x) & 0x3ff) << 0)
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#define ANDES_SPI_DCR_DYCNT(x) (((x) & 0x7) << 12)
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#define ANDES_SPI_DCR_WCNT(x) (((x) & 0x3ff) << 16)
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#define ANDES_SPI_DCR_TRAMODE(x) (((x) & 0x7) << 28)
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#define ANDES_SPI_DCR_SPIT BIT(31) /* SPI bus trigger */
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#define ANDES_SPI_DCR_MODE_WRCON ANDES_SPI_DCR_TRAMODE(0) /* w/r at the same time */
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#define ANDES_SPI_DCR_MODE_WO ANDES_SPI_DCR_TRAMODE(1) /* write only */
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#define ANDES_SPI_DCR_MODE_RO ANDES_SPI_DCR_TRAMODE(2) /* read only */
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#define ANDES_SPI_DCR_MODE_WR ANDES_SPI_DCR_TRAMODE(3) /* write, read */
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#define ANDES_SPI_DCR_MODE_RW ANDES_SPI_DCR_TRAMODE(4) /* read, write */
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#define ANDES_SPI_DCR_MODE_WDR ANDES_SPI_DCR_TRAMODE(5) /* write, dummy, read */
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#define ANDES_SPI_DCR_MODE_RDW ANDES_SPI_DCR_TRAMODE(6) /* read, dummy, write */
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#define ANDES_SPI_DCR_MODE_RECEIVE ANDES_SPI_DCR_TRAMODE(7) /* receive */
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/* 0x20 - AHB SPI interface setting register */
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#define ANDES_SPI_AHB_BAUD(x) (((x) & 0xff) < 0)
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#define ANDES_SPI_AHB_CSHT(x) (((x) & 0xf) < 16)
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#define ANDES_SPI_AHB_SPNTS BIT(20) /* 0: normal, 1: delay */
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#define ANDES_SPI_AHB_CPHA BIT(24) /* 0: Sampling at odd edges */
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#define ANDES_SPI_AHB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
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#define ANDES_SPI_AHB_MSSL BIT(26) /* only Master mode */
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/* 0x3c - Version Register - (Year V.MAJOR.MINOR) */
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#define ANDES_SPI_VER_MINOR(x) (((x) >> 0) & 0xf)
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#define ANDES_SPI_VER_MAJOR(x) (((x) >> 8) & 0xf)
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#define ANDES_SPI_VER_YEAR(x) (((x) >> 16) & 0xf)
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||||||
struct andes_spi_slave {
|
|
||||||
struct spi_slave slave;
|
|
||||||
struct andes_spi_regs *regs;
|
|
||||||
unsigned int freq;
|
|
||||||
};
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|
||||||
|
|
||||||
static inline struct andes_spi_slave *to_andes_spi(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
return container_of(slave, struct andes_spi_slave, slave);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __ANDES_SPI_H */
|
|
||||||
Loading…
Reference in New Issue
Block a user