arm: dts: meson: import dts files from Linux 4.12
Import Amlogic Meson DTS files from Linux kernel version 4.12 Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Beniamino Galvani
Tom Rini
parent
609bf92411
commit
4a63a75c83
@ -71,6 +71,14 @@
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reg = <0x0 0x10000000 0x0 0x200000>;
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no-map;
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};
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0xbc00000>;
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alignment = <0x0 0x400000>;
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linux,cma-default;
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};
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};
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cpus {
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@ -233,7 +241,7 @@
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};
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i2c_A: i2c@8500 {
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compatible = "amlogic,meson-gxbb-i2c";
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compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
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reg = <0x0 0x08500 0x0 0x20>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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@ -255,6 +263,14 @@
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status = "disabled";
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};
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saradc: adc@8680 {
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compatible = "amlogic,meson-saradc";
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reg = <0x0 0x8680 0x0 0x34>;
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#io-channel-cells = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
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reg = <0x0 0x086c0 0x0 0x10>;
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@ -271,7 +287,7 @@
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};
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i2c_B: i2c@87c0 {
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compatible = "amlogic,meson-gxbb-i2c";
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compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
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reg = <0x0 0x087c0 0x0 0x20>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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@ -280,7 +296,7 @@
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};
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i2c_C: i2c@87e0 {
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compatible = "amlogic,meson-gxbb-i2c";
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compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
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reg = <0x0 0x087e0 0x0 0x20>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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@ -288,6 +304,14 @@
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status = "disabled";
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};
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spifc: spi@8c80 {
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compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
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reg = <0x0 0x08c80 0x0 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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watchdog@98d0 {
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compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
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reg = <0x0 0x098d0 0x0 0x10>;
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@ -309,7 +333,7 @@
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};
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sram: sram@c8000000 {
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compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
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compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
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reg = <0x0 0xc8000000 0x0 0x14000>;
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#address-cells = <1>;
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@ -317,12 +341,12 @@
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ranges = <0 0x0 0xc8000000 0x14000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "amlogic,meson-gxbb-scp-shmem";
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compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
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reg = <0x13000 0x400>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "amlogic,meson-gxbb-scp-shmem";
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compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
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reg = <0x13400 0x400>;
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};
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};
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@ -334,6 +358,13 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
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reg = <0x0 0x00040 0x0 0x4>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x004c0 0x0 0x14>;
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@ -350,8 +381,24 @@
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status = "disabled";
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};
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i2c_AO: i2c@500 {
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compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
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reg = <0x0 0x500 0x0 0x20>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm_AO_ab: pwm@550 {
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compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
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reg = <0x0 0x00550 0x0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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ir: ir@580 {
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compatible = "amlogic,meson-gxbb-ir";
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compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
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reg = <0x0 0x00580 0x0 0x40>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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@ -365,13 +412,12 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
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rng {
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hwrng: rng {
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compatible = "amlogic,meson-rng";
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reg = <0x0 0x0 0x0 0x4>;
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};
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};
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hiubus: hiubus@c883c000 {
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compatible = "simple-bus";
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reg = <0x0 0xc883c000 0x0 0x2000>;
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@ -395,7 +441,6 @@
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0x0 0xc8834540 0x0 0x4>;
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interrupts = <0 8 1>;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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status = "disabled";
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};
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@ -442,6 +487,38 @@
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cvbs_vdac_port: port@0 {
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reg = <0>;
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};
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/* HDMI-TX output port */
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hdmi_tx_port: port@1 {
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reg = <1>;
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hdmi_tx_out: endpoint {
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remote-endpoint = <&hdmi_tx_in>;
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};
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};
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};
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hdmi_tx: hdmi-tx@c883a000 {
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compatible = "amlogic,meson-gx-dw-hdmi";
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reg = <0x0 0xc883a000 0x0 0x1c>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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/* VPU VENC Input */
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hdmi_tx_venc_port: port@0 {
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reg = <0>;
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hdmi_tx_in: endpoint {
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remote-endpoint = <&hdmi_tx_out>;
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};
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};
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/* TMDS Output */
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hdmi_tx_tmds_port: port@1 {
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reg = <1>;
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};
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};
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};
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};
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@ -50,7 +50,7 @@
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/ {
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compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
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model = "Hardkernel ODROID-C2";
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aliases {
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serial0 = &uart_AO;
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};
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@ -96,7 +96,7 @@
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
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gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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@ -152,6 +152,13 @@
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pinctrl-0 = <ð_rgmii_pins>;
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pinctrl-names = "default";
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phy-handle = <ð_phy0>;
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phy-mode = "rgmii";
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snps,reset-gpio = <&gpio GPIOZ_14 0>;
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snps,reset-delays-us = <0 10000 1000000>;
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snps,reset-active-low;
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amlogic,tx-delay-ns = <2>;
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mdio {
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compatible = "snps,dwmac-mdio";
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@ -165,6 +172,57 @@
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};
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};
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&pinctrl_aobus {
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gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
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"USB HUB nRESET", "USB OTG Power En",
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"J7 Header Pin2", "IR In", "J7 Header Pin4",
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"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
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"HDMI CEC", "SYS LED";
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};
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&pinctrl_periphs {
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gpio-line-names = /* Bank GPIOZ */
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"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
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"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
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"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
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"Eth PHY nRESET", "Eth PHY Intc",
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/* Bank GPIOH */
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"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
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/* Bank BOOT */
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"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
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"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
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"eMMC Reset", "eMMC CMD",
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"", "", "", "", "", "", "",
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/* Bank CARD */
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"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
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"SDCard D3", "SDCard D2", "SDCard Det",
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/* Bank GPIODV */
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"", "", "", "", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "", "",
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"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
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"PWM D", "PWM B",
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/* Bank GPIOY */
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"Revision Bit0", "Revision Bit1", "",
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"J2 Header Pin35", "", "", "", "J2 Header Pin36",
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"J2 Header Pin31", "", "", "", "TF VDD En",
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"J2 Header Pin32", "J2 Header Pin26", "", "",
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/* Bank GPIOX */
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"J2 Header Pin29", "J2 Header Pin24",
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"J2 Header Pin23", "J2 Header Pin22",
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"J2 Header Pin21", "J2 Header Pin18",
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"J2 Header Pin33", "J2 Header Pin19",
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"J2 Header Pin16", "J2 Header Pin15",
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"J2 Header Pin12", "J2 Header Pin13",
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"J2 Header Pin8", "J2 Header Pin10",
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"", "", "", "", "",
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"J2 Header Pin11", "", "J2 Header Pin7",
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/* Bank GPIOCLK */
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"", "", "", "",
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/* GPIO_TEST_N */
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"";
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};
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&ir {
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status = "okay";
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pinctrl-0 = <&remote_input_ao_pins>;
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@ -177,6 +235,21 @@
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pinctrl-names = "default";
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};
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&gpio_ao {
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/*
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* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
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* to be turned high in order to be detected by the USB Controller
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* This signal should be handled by a USB specific power sequence
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* in order to reset the Hub when USB bus is powered down.
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*/
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usb-hub {
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gpio-hog;
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gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-hub-reset";
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};
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};
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&usb0_phy {
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status = "okay";
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phy-supply = <&usb_otg_pwr>;
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@ -194,6 +267,11 @@
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status = "okay";
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};
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&saradc {
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status = "okay";
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vref-supply = <&vcc1v8>;
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};
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/* SD */
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&sd_emmc_b {
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status = "okay";
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@ -97,17 +97,6 @@
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};
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};
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&cbus {
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spifc: spi@8c80 {
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compatible = "amlogic,meson-gxbb-spifc";
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reg = <0x0 0x08c80 0x0 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkc CLKID_SPI>;
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status = "disabled";
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};
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};
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ðmac {
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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@ -129,6 +118,7 @@
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 14>;
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};
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uart_ao_a_pins: uart_ao_a {
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@ -203,30 +193,62 @@
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function = "pwm_ao_b";
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};
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};
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};
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gxbb-aoclkc";
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reg = <0x0 0x00040 0x0 0x4>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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i2s_am_clk_pins: i2s_am_clk {
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mux {
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groups = "i2s_am_clk";
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function = "i2s_out_ao";
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};
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};
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pwm_ab_AO: pwm@550 {
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compatible = "amlogic,meson-gxbb-pwm";
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reg = <0x0 0x0550 0x0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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i2s_out_ao_clk_pins: i2s_out_ao_clk {
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mux {
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groups = "i2s_out_ao_clk";
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function = "i2s_out_ao";
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};
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};
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i2c_AO: i2c@500 {
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compatible = "amlogic,meson-gxbb-i2c";
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reg = <0x0 0x500 0x0 0x20>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkc CLKID_AO_I2C>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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i2s_out_lr_clk_pins: i2s_out_lr_clk {
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mux {
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groups = "i2s_out_lr_clk";
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function = "i2s_out_ao";
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};
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};
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i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
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mux {
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groups = "i2s_out_ch01_ao";
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function = "i2s_out_ao";
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};
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};
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i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
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mux {
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groups = "i2s_out_ch23_ao";
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function = "i2s_out_ao";
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};
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};
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i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
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mux {
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groups = "i2s_out_ch45_ao";
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function = "i2s_out_ao";
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};
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};
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spdif_out_ao_6_pins: spdif_out_ao_6 {
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mux {
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groups = "spdif_out_ao_6";
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function = "spdif_out_ao";
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};
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};
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spdif_out_ao_13_pins: spdif_out_ao_13 {
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mux {
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groups = "spdif_out_ao_13";
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function = "spdif_out_ao";
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};
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};
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};
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};
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@ -245,6 +267,7 @@
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_periphs 0 14 120>;
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};
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emmc_pins: emmc {
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@ -467,6 +490,34 @@
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function = "hdmi_i2c";
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};
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};
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i2sout_ch23_y_pins: i2sout_ch23_y {
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mux {
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groups = "i2sout_ch23_y";
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function = "i2s_out";
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};
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};
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i2sout_ch45_y_pins: i2sout_ch45_y {
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mux {
|
||||
groups = "i2sout_ch45_y";
|
||||
function = "i2s_out";
|
||||
};
|
||||
};
|
||||
|
||||
i2sout_ch67_y_pins: i2sout_ch67_y {
|
||||
mux {
|
||||
groups = "i2sout_ch67_y";
|
||||
function = "i2s_out";
|
||||
};
|
||||
};
|
||||
|
||||
spdif_out_y_pins: spdif_out_y {
|
||||
mux {
|
||||
groups = "spdif_out_y";
|
||||
function = "spdif_out";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -478,10 +529,51 @@
|
||||
};
|
||||
};
|
||||
|
||||
&apb {
|
||||
mali: gpu@c0000 {
|
||||
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
|
||||
reg = <0x0 0xc0000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gp", "gpmmu", "pp", "pmu",
|
||||
"pp0", "ppmmu0", "pp1", "ppmmu1",
|
||||
"pp2", "ppmmu2";
|
||||
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
|
||||
clock-names = "bus", "core";
|
||||
|
||||
/*
|
||||
* Mali clocking is provided by two identical clock paths
|
||||
* MALI_0 and MALI_1 muxed to a single clock by a glitch
|
||||
* free mux to safely change frequency while running.
|
||||
*/
|
||||
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
|
||||
<&clkc CLKID_MALI_0>,
|
||||
<&clkc CLKID_MALI>; /* Glitch free mux */
|
||||
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_MALI_0>;
|
||||
assigned-clock-rates = <0>, /* Do Nothing */
|
||||
<666666666>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_A {
|
||||
clocks = <&clkc CLKID_I2C>;
|
||||
};
|
||||
|
||||
&i2c_AO {
|
||||
clocks = <&clkc CLKID_AO_I2C>;
|
||||
};
|
||||
|
||||
&i2c_B {
|
||||
clocks = <&clkc CLKID_I2C>;
|
||||
};
|
||||
@ -490,6 +582,16 @@
|
||||
clocks = <&clkc CLKID_I2C>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
|
||||
clocks = <&xtal>,
|
||||
<&clkc CLKID_SAR_ADC>,
|
||||
<&clkc CLKID_SANA>,
|
||||
<&clkc CLKID_SAR_ADC_CLK>,
|
||||
<&clkc CLKID_SAR_ADC_SEL>;
|
||||
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
|
||||
};
|
||||
|
||||
&sd_emmc_a {
|
||||
clocks = <&clkc CLKID_SD_EMMC_A>,
|
||||
<&xtal>,
|
||||
@ -511,6 +613,27 @@
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&spifc {
|
||||
clocks = <&clkc CLKID_SPI>;
|
||||
};
|
||||
|
||||
&vpu {
|
||||
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
|
||||
};
|
||||
|
||||
&hwrng {
|
||||
clocks = <&clkc CLKID_RNG0>;
|
||||
clock-names = "core";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
|
||||
resets = <&reset RESET_HDMITX_CAPB3>,
|
||||
<&reset RESET_HDMI_SYSTEM_RESET>,
|
||||
<&reset RESET_HDMI_TX>;
|
||||
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
|
||||
clocks = <&clkc CLKID_HDMI_PCLK>,
|
||||
<&clkc CLKID_CLK81>,
|
||||
<&clkc CLKID_GCLK_VENCI_INT0>;
|
||||
clock-names = "isfr", "iahb", "venci";
|
||||
};
|
||||
|
||||
@ -5,30 +5,50 @@
|
||||
#ifndef __GXBB_CLKC_H
|
||||
#define __GXBB_CLKC_H
|
||||
|
||||
#define CLKID_CPUCLK 1
|
||||
#define CLKID_HDMI_PLL 2
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
#define CLKID_FCLK_DIV4 6
|
||||
#define CLKID_GP0_PLL 9
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_MPLL2 15
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_AO_I2C 93
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
#define CLKID_SD_EMMC_C 96
|
||||
#define CLKID_SAR_ADC_CLK 97
|
||||
#define CLKID_SAR_ADC_SEL 98
|
||||
#define CLKID_MALI_0_SEL 100
|
||||
#define CLKID_MALI_0 102
|
||||
#define CLKID_MALI_1_SEL 103
|
||||
#define CLKID_MALI_1 105
|
||||
#define CLKID_MALI 106
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_I958 113
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user