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* Patch by Matthew S. McClintock, 14 Apr 2004:

Browse Source 
fix initdram function for utx8245 board

* Patch by Markus Pietrek, 14 Apr 2004:
  use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag

* Patch by Reinhard Meyer, 18 Apr 2004:
  provide the IDE Reset Function for EMK 5200 boards

* Patch by Masami Komiya, 12 Apr 2004:
  fix pci_hose_write_config_{byte,word}_via_dword problems
This commit is contained in:
wdenk
2004-04-18 22:26:17 +00:00
parent a8bd82de46
commit 498b8db7f5
6 changed files with 52 additions and 33 deletions
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28
board/emk/top5200/top5200.c
View File

@@ -182,21 +182,29 @@ void pci_init_board(void)
#endif
/*****************************************************************************
* provide the PCI Reset Function
* provide the IDE Reset Function
*****************************************************************************/
#ifdef CFG_CMD_IDE
#define GPIO_PSC1_4 0x01000000ul
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
} else {
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
}
/* Configure PSC1_4 as GPIO output for ATA reset */
/* (it does not matter we do this every time) */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}
#endif
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */

27
board/utx8245/utx8245.c
View File

@@ -48,35 +48,30 @@ int checkboard(void)
long int initdram(int board_type)
{
#if 1
long size;
long new_bank0_end;
long new_bank1_end;
long mear1;
long emear1;
/*
write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
*/
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
new_bank0_end = size - 1;
new_bank0_end = size/2 - 1;
new_bank1_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mear1 = (mear1 & 0xFFFF0000) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8);
emear1 = (emear1 & 0xFFFF0000) |
((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
return (size);
#else
return (CFG_MAX_RAM_SIZE);
#endif
}