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riscv: Fix context restore before returning from trap handler

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sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Bin Meng 2018-12-12 06:12:42 -08:00 committed by Andes
parent 4b3f5ed5ac
commit 496262cca6
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/cpu/mtrap.S
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@ -77,7 +77,6 @@ trap_entry:
#endif
csrs MODE_PREFIX(status), t0
LREG x1, 1 * REGBYTES(sp)
LREG x2, 2 * REGBYTES(sp)
LREG x3, 3 * REGBYTES(sp)
LREG x4, 4 * REGBYTES(sp)
LREG x5, 5 * REGBYTES(sp)
@ -107,5 +106,6 @@ trap_entry:
LREG x29, 29 * REGBYTES(sp)
LREG x30, 30 * REGBYTES(sp)
LREG x31, 31 * REGBYTES(sp)
LREG x2, 2 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
MODE_PREFIX(ret)