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Merge with /home/stefan/git/u-boot/denx

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This commit is contained in:
Stefan Roese 2006-11-27 14:11:22 +01:00
commit 48c7d6dba9
10 changed files with 291 additions and 115 deletions
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93
CHANGELOG
View File

@ -1,6 +1,99 @@
<<<<<<< master
======================================================================
Changes since U-Boot 1.1.4:
======================================================================
=======
commit 260421a21e934a68d31fb6125b0fbd2631a8ca20
Author: Stefan Roese <sr@denx.de>
Date: Mon Nov 13 13:55:24 2006 +0100
[PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated]
* Adds support for AMD command set Top Boot flash geometry reversal
* Adds support for reading JEDEC Manufacturer ID and Device ID
* Adds support for displaying command set, manufacturer id and
device ids (flinfo)
* Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined
* Removes outdated change history (refer to git log instead)
Signed-off-by: Tolunay Orkun <listmember@orkun.us>
Signed-off-by: Stefan Roese <sr@denx.de>
commit b21b511d4c50408f4853f46f06b601272196223f
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun Nov 12 21:13:23 2006 +0100
Update CHANGELOG
commit ce3f1a40c507afbab06c5eb58ccdc6713eda3245
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Sat Nov 11 22:48:22 2006 +0100
Disable the watchdog in the default config for the V38B board.
commit 44a47e6db2694841211f1c8fdbafd36992e9cd1a
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Sat Nov 11 22:43:00 2006 +0100
Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin
group is enabled for USB earlier (in cpu_init_f() instead of
usb_lowlevel_init()).
commit 91650b3e4de688038d4f71279c44858e3e2c6870
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Mon Nov 6 17:06:36 2006 +0100
Sequential accesses to non-existent memory must be synchronized,
at least on G2 cores.
This fixes get_ram_size() problems on MPC5200 Rev. B boards.
commit c59200443072353044aa4bf737a5a60f9a9af231
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu Nov 2 15:15:01 2006 +0100
Release U-Boot 1.1.6
commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Nov 1 02:04:38 2006 +0100
Finish up support for MarelV38B board
- add watchdog support
- enable GPIO_WKUP_7 pin for input
- code cleanup
commit ffa150bc90c943ca265170bd1be3f293674dd5c7
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Nov 1 01:45:46 2006 +0100
- Fix issues related to the use of ELDK 4 when compiling for MarelV38B:
* remove warnings when compiling ethaddr.c
* adjust linker script (fixes a crash resulting from incorrect
definition of __u_boot_cmd_start)
- Some MarelV38B code cleanup.
commit dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Nov 1 01:38:16 2006 +0100
- Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the
MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's
Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with
MPC5XXX_WU_GPIO_DATA_O for affected boards.
- Add defintions for some MPC5XXX GPIO pins.
commit 82d9c9ec29a1bec1b03ba616425ebaed231072c8
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Nov 1 01:34:29 2006 +0100
Changed MarelV38B board make target to lowercase. Config file cleanup.
commit 1954be6e9c9421b45d0a9d05b10356acc7563150
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun Oct 29 01:03:51 2006 +0200
>>>>>>> origin
* CFG_NAND_QUIET_TEST added to not warn upon missing NAND device
Patch by Stefan Roese, 07 Oct 2006

2
MAKEALL
View File

@ -88,7 +88,7 @@ LIST_4xx=" \
PMC405 PPChameleonEVB sbc405 sequoia \
sequoia_nand VOH405 VOM405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite yucca bamboo \
yellowstone yosemite yucca \
"
#########################################################################

2
board/tqm5200/cam5200_flash.c
View File

@ -759,7 +759,7 @@ unsigned long flash_init(void)
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
i+1, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}

2
board/tqm5200/tqm5200.c
View File

@ -289,7 +289,7 @@ int checkboard (void)
#elif defined(CONFIG_TB5200)
# define CARRIER_NAME "TB5200"
#elif defined(CONFIG_CAM5200)
# define CARRIER_NAME "Cam5200"
# define CARRIER_NAME "CAM5200"
#elif defined(CONFIG_FO300)
# define CARRIER_NAME "FO300"
#else

23
cpu/ppc4xx/start.S
View File

@ -204,6 +204,18 @@ _start_440:
mfspr r1,mcsr
mtspr mcsr,r1
#endif
/*----------------------------------------------------------------*/
/* CCR0 init */
/*----------------------------------------------------------------*/
/* Disable store gathering & broadcast, guarantee inst/data
* cache block touch, force load/store alignment
* (see errata 1.12: 440_33)
*/
lis r1,0x0030 /* store gathering & broadcast disable */
ori r1,r1,0x6000 /* cache touch */
mtspr ccr0,r1
/*----------------------------------------------------------------*/
/* Initialize debug */
/*----------------------------------------------------------------*/
@ -225,17 +237,6 @@ _start_440:
mtspr dbsr,r1 /* Clear all valid bits */
skip_debug_init:
/*----------------------------------------------------------------*/
/* CCR0 init */
/*----------------------------------------------------------------*/
/* Disable store gathering & broadcast, guarantee inst/data
* cache block touch, force load/store alignment
* (see errata 1.12: 440_33)
*/
lis r1,0x0030 /* store gathering & broadcast disable */
ori r1,r1,0x6000 /* cache touch */
mtspr ccr0,r1
#if defined (CONFIG_440SPE)
/*----------------------------------------------------------------+
| Initialize Core Configuration Reg1.

214
drivers/cfi_flash.c
View File

@ -4,11 +4,12 @@
*
* Copyright (C) 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
* Modified to work with AMD flashes
*
* Copyright (C) 2004
* Ed Okerson
* Modified to work with little-endian systems.
*
* Copyright (C) 2006
* Tolunay Orkun <listmember@orkun.us>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -28,17 +29,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* History
* 01/20/2004 - combined variants of original driver.
* 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
* 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
* 01/27/2004 - Little endian support Ed Okerson
*
* Tested Architectures
* Port Width Chip Width # of banks Flash Chip Board
* 32 16 1 28F128J3 seranoa/eagle
* 64 16 1 28F128J3 seranoa/falcon
*
*/
/* The DEBUG define must be before common to enable debugging */
@ -54,21 +44,16 @@
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
* The width of the port and the width of the chips are determined at initialization.
* These widths are used to calculate the address for access CFI data structures.
* It has been tested on an Intel Strataflash implementation and AMD 29F016D.
*
* References
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
* AMD CFI Specification, Release 2.0 December 1, 2001
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
* TODO
*
* Use Primary Extended Query table (PRI) and Alternate Algorithm Query
* Table (ALT) to determine if protection is available
*
* Add support for other command sets Use the PRI and ALT to determine command set
* Verify erase and program timeouts.
*/
#ifndef CFG_FLASH_BANKS_LIST
@ -114,6 +99,10 @@
#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
#define FLASH_OFFSET_MANUFACTURER_ID 0x00
#define FLASH_OFFSET_DEVICE_ID 0x01
#define FLASH_OFFSET_DEVICE_ID2 0x0E
#define FLASH_OFFSET_DEVICE_ID3 0x0F
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_RESP 0x10
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
@ -135,25 +124,20 @@
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
#define FLASH_MAN_CFI 0x01000000
#define CFI_CMDSET_NONE 0
#define CFI_CMDSET_INTEL_EXTENDED 1
#define CFI_CMDSET_AMD_STANDARD 2
#define CFI_CMDSET_INTEL_STANDARD 3
#define CFI_CMDSET_AMD_EXTENDED 4
#define CFI_CMDSET_MITSU_STANDARD 256
#define CFI_CMDSET_MITSU_EXTENDED 257
#define CFI_CMDSET_SST 258
#define CFI_CMDSET_NONE 0
#define CFI_CMDSET_INTEL_EXTENDED 1
#define CFI_CMDSET_AMD_STANDARD 2
#define CFI_CMDSET_INTEL_STANDARD 3
#define CFI_CMDSET_AMD_EXTENDED 4
#define CFI_CMDSET_MITSU_STANDARD 256
#define CFI_CMDSET_MITSU_EXTENDED 257
#define CFI_CMDSET_SST 258
#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef FLASH_CMD_RESET
# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
#endif
typedef union {
unsigned char c;
unsigned short w;
@ -168,7 +152,7 @@ typedef union {
volatile unsigned long long *llp;
} cfiptr_t;
#define NUM_ERASE_REGIONS 4
#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
@ -200,6 +184,7 @@ static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static void flash_read_jedec_ids (flash_info_t * info);
static int flash_detect_cfi (flash_info_t * info);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
@ -307,7 +292,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
}
/*-----------------------------------------------------------------------
* read a long word by picking the least significant byte of each maiximum
* read a long word by picking the least significant byte of each maximum
* port size word. Swap for ppc format.
*/
ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
@ -529,14 +514,42 @@ void flash_print_info (flash_info_t * info)
(info->portwidth << 3), (info->chipwidth << 3));
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
printf (" ");
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
printf ("Intel Standard");
break;
case CFI_CMDSET_INTEL_EXTENDED:
printf ("Intel Extended");
break;
case CFI_CMDSET_AMD_STANDARD:
printf ("AMD Standard");
break;
case CFI_CMDSET_AMD_EXTENDED:
printf ("AMD Extended");
break;
default:
printf ("Unknown (%d)", info->vendor);
break;
}
printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X",
info->manufacturer_id, info->device_id);
if (info->device_id == 0x7E) {
printf("%04X", info->device_id2);
}
printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
info->erase_blk_tout,
info->write_tout,
info->write_tout);
if (info->buffer_size > 1) {
printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n",
info->buffer_write_tout,
info->buffer_size);
}
puts (" Sector Start Addresses:");
puts ("\n Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n");
#ifdef CFG_FLASH_EMPTY_INFO
int k;
int size;
@ -560,18 +573,15 @@ void flash_print_info (flash_info_t * info)
}
}
if ((i % 5) == 0)
printf ("\n");
/* print empty and read-only info */
printf (" %08lX%s%s",
printf (" %08lX %c %s ",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
erased ? 'E' : ' ',
info->protect[i] ? "RO" : " ");
#else /* ! CFG_FLASH_EMPTY_INFO */
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
printf (" %08lX %s ",
info->start[i],
info->protect[i] ? "RO" : " ");
#endif
}
putc ('\n');
@ -1070,6 +1080,55 @@ static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uc
return retval;
}
/*-----------------------------------------------------------------------
* read jedec ids from device and set corresponding fields in info struct
*
* Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
*
*/
static void flash_read_jedec_ids (flash_info_t * info)
{
info->manufacturer_id = 0;
info->device_id = 0;
info->device_id2 = 0;
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
udelay(1000); /* some flash are slow to respond */
info->manufacturer_id = flash_read_uchar (info,
FLASH_OFFSET_MANUFACTURER_ID);
info->device_id = flash_read_uchar (info,
FLASH_OFFSET_DEVICE_ID);
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID);
udelay(1000); /* some flash are slow to respond */
info->manufacturer_id = flash_read_uchar (info,
FLASH_OFFSET_MANUFACTURER_ID);
info->device_id = flash_read_uchar (info,
FLASH_OFFSET_DEVICE_ID);
if (info->device_id == 0x7E) {
/* AMD 3-byte (expanded) device ids */
info->device_id2 = flash_read_uchar (info,
FLASH_OFFSET_DEVICE_ID2);
info->device_id2 <<= 8;
info->device_id2 |= flash_read_uchar (info,
FLASH_OFFSET_DEVICE_ID3);
}
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
break;
default:
break;
}
}
/*-----------------------------------------------------------------------
* detect if flash is compatible with the Common Flash Interface (CFI)
* http://www.jedec.org/download/search/jesd68.pdf
@ -1120,15 +1179,31 @@ ulong flash_get_size (ulong base, int banknum)
uchar num_erase_regions;
int erase_region_size;
int erase_region_count;
int geometry_reversed = 0;
info->ext_addr = 0;
info->cfi_version = 0;
#ifdef CFG_FLASH_PROTECTION
int ext_addr;
info->legacy_unlock = 0;
#endif
info->start[0] = base;
if (flash_detect_cfi (info)) {
info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
info->vendor = flash_read_ushort (info, 0,
FLASH_OFFSET_PRIMARY_VENDOR);
flash_read_jedec_ids (info);
flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
num_erase_regions = flash_read_uchar (info,
FLASH_OFFSET_NUM_ERASE_REGIONS);
info->ext_addr = flash_read_ushort (info, 0,
FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
if (info->ext_addr) {
info->cfi_version = (ushort) flash_read_uchar (info,
info->ext_addr + 3) << 8;
info->cfi_version |= (ushort) flash_read_uchar (info,
info->ext_addr + 4);
}
#ifdef DEBUG
flash_printqry (info, 0);
#endif
@ -1139,26 +1214,46 @@ ulong flash_get_size (ulong base, int banknum)
info->cmd_reset = FLASH_CMD_RESET;
#ifdef CFG_FLASH_PROTECTION
/* read legacy lock/unlock bit from intel flash */
ext_addr = flash_read_ushort (info, 0,
FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
info->legacy_unlock =
flash_read_uchar (info, ext_addr + 5) & 0x08;
if (info->ext_addr) {
info->legacy_unlock = flash_read_uchar (info,
info->ext_addr + 5) & 0x08;
}
#endif
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
info->cmd_reset = AMD_CMD_RESET;
/* check if flash geometry needs reversal */
if (num_erase_regions <= 1)
break;
/* reverse geometry if top boot part */
if (info->cfi_version < 0x3131) {
/* CFI < 1.1, try to guess from device id */
if ((info->device_id & 0x80) != 0) {
geometry_reversed = 1;
}
break;
}
/* CFI >= 1.1, deduct from top/bottom flag */
/* note: ext_addr is valid since cfi_version > 0 */
if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
geometry_reversed = 1;
}
break;
}
debug ("manufacturer is %d\n", info->vendor);
debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
debug ("device id is 0x%x\n", info->device_id);
debug ("device id2 is 0x%x\n", info->device_id2);
debug ("cfi version is 0x%04x\n", info->cfi_version);
size_ratio = info->portwidth / info->chipwidth;
/* if the chip is x8/x16 reduce the ratio by half */
if ((info->interface == FLASH_CFI_X8X16)
&& (info->chipwidth == FLASH_CFI_BY8)) {
size_ratio >>= 1;
}
num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
debug ("size_ratio %d port %d bits chip %d bits\n",
size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
@ -1171,7 +1266,12 @@ ulong flash_get_size (ulong base, int banknum)
num_erase_regions, NUM_ERASE_REGIONS);
break;
}
tmp = flash_read_long (info, 0,
if (geometry_reversed)
tmp = flash_read_long (info, 0,
FLASH_OFFSET_ERASE_REGIONS +
(num_erase_regions - 1 - i) * 4);
else
tmp = flash_read_long (info, 0,
FLASH_OFFSET_ERASE_REGIONS +
i * 4);
erase_region_size =

46
include/configs/TQM5200.h
View File

@ -217,43 +217,19 @@
#undef CONFIG_BOOTARGS
#ifdef CONFIG_STK52XX
# if defined(CONFIG_TQM5200_B)
# if defined(CFG_LOWBOOT)
# define ENV_UPDT \
"update=protect off FC000000 FC07FFFF;" \
"erase FC000000 FC07FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC07FFFF\0"
# else /* highboot */
# define ENV_UPDT \
"update=protect off FFF00000 FFF7FFFF;" \
"erase FFF00000 FFF7FFFF;" \
#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT)
# define ENV_UPDT \
"update=protect off FFF00000 +${filesize};" \
"erase FFF00000 +${filesize};" \
"cp.b 200000 FFF00000 ${filesize};" \
"protect on FFF00000 FFF7FFFF\0"
# endif /* CFG_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
# define ENV_UPDT \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
"protect on FFF00000 +${filesize}\0"
#else /* default lowboot configuration */
# define ENV_UPDT \
"update=protect off FC000000 FC03FFFF;" \
"erase FC000000 FC03FFFF;" \
"update=protect off FC000000 +${filesize};" \
"erase FC000000 +${filesize};" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC03FFFF\0"
#elif defined (CONFIG_FO300)
# define ENV_UPDT \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0"
#else
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
"protect on FC000000 +${filesize}\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
@ -432,7 +408,7 @@
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
#if defined(CONFIG_TQM5200_B)
#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
#define CFG_ENV_SECT_SIZE 0x40000
#else
#define CFG_ENV_SECT_SIZE 0x20000

12
include/configs/sequoia.h
View File

@ -53,7 +53,7 @@
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
@ -234,10 +234,10 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/sequoia/uImage\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE180000\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
@ -378,7 +378,7 @@
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000)
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
@ -387,7 +387,7 @@
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 3 (NOR-FLASH) initialization */
#define CFG_EBC_PB3AP 0x03017300
#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000)
#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000)
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CFG_EBC_PB0AP 0x018003c0

4
include/configs/v38b.h
View File

@ -34,7 +34,7 @@
#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
#define CONFIG_HW_WATCHDOG 1 /* has watchdog */
#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
#define CONFIG_NETCONSOLE 1
@ -246,7 +246,7 @@
/*
* GPIO configuration
*/
#define CFG_GPS_PORT_CONFIG 0x90000404
#define CFG_GPS_PORT_CONFIG 0x90001404
/*
* Miscellaneous configurable options

8
include/flash.h
View File

@ -43,9 +43,14 @@ typedef struct {
ulong write_tout; /* maximum write timeout */
ulong buffer_write_tout; /* maximum buffer write timeout */
ushort vendor; /* the primary vendor id */
ushort cmd_reset; /* Vendor specific reset command */
ushort cmd_reset; /* vendor specific reset command */
ushort interface; /* used for x8/x16 adjustments */
ushort legacy_unlock; /* support Intel legacy (un)locking */
uchar manufacturer_id; /* manufacturer id */
ushort device_id; /* device id */
ushort device_id2; /* extended device id */
ushort ext_addr; /* extended query table address */
ushort cfi_version; /* cfi version */
#endif
} flash_info_t;
@ -439,6 +444,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FLASH_MAN_MT 0x00400000
#define FLASH_MAN_SHARP 0x00500000
#define FLASH_MAN_ATM 0x00600000
#define FLASH_MAN_CFI 0x01000000
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */