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imx: imx8mp_evk: enable eth support

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Add board code to configure the network interface
Add net defconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
2020-12-25 16:16:34 +08:00
committed by Stefano Babic
parent 184aa65041
commit 48b90f86c5
5 changed files with 94 additions and 2 deletions
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65
board/freescale/imx8mp_evk/imx8mp_evk.c
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@@ -7,9 +7,13 @@
#include <env.h>
#include <errno.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/delay.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
@@ -40,9 +44,68 @@ int board_early_init_f(void)
return 0;
}
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(22));
}
#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
static iomux_v3_cfg_t const eqos_rst_pads[] = {
MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_eqos(void)
{
imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
ARRAY_SIZE(eqos_rst_pads));
gpio_request(EQOS_RST_PAD, "eqos_rst");
gpio_direction_output(EQOS_RST_PAD, 0);
mdelay(15);
gpio_direction_output(EQOS_RST_PAD, 1);
mdelay(100);
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_eqos();
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if CONFIG_IS_ENABLED(NET)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
return 0;
int ret = 0;
if (CONFIG_IS_ENABLED(FEC_MXC)) {
setup_fec();
if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
ret = setup_eqos();
}
return ret;
}
int board_late_init(void)