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Blackfin: add workaround for anomaly 05000242

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DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.

WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2009-04-04 08:10:22 -04:00
parent ce1fe4ba6b
commit 48ab150925
1 changed files with 1 additions and 1 deletions
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2
cpu/blackfin/initcode.c
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@ -401,7 +401,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
serial_putc('!');
bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
asm("idle;");