Convert CONFIG_SYS_NAND_5_ADDR_CYCLE to Kconfig
This converts the following to Kconfig: CONFIG_SYS_NAND_5_ADDR_CYCLE Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
9d9f59dd0a
commit
4884d829d7
@ -57,6 +57,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_ADDR=31
|
||||
|
@ -425,6 +425,15 @@ config SYS_NAND_MAX_CHIPS
|
||||
|
||||
if SPL
|
||||
|
||||
config SYS_NAND_5_ADDR_CYCLE
|
||||
bool "Wait 5 address cycles during NAND commands"
|
||||
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
|
||||
(SPL_NAND_SUPPORT && NAND_ATMEL)
|
||||
default y
|
||||
help
|
||||
Some controllers require waiting for 5 address cycles when issuing
|
||||
some commands, on NAND chips larger than 128MiB.
|
||||
|
||||
choice
|
||||
prompt "NAND bad block marker/indicator positon in the OOB"
|
||||
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
|
||||
|
@ -180,7 +180,6 @@
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -106,9 +106,6 @@
|
||||
#define CONFIG_SYS_BOOTCOUNT_LE
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
|
||||
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
|
||||
|
@ -106,7 +106,6 @@
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION 1
|
||||
|
||||
/* NAND config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -19,7 +19,6 @@
|
||||
|
||||
/* Board NAND Info. */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
|
||||
11, 12, 13, 14, 16, 17, 18, 19, 20, \
|
||||
21, 22, 23, 24, 25, 26, 27, 28, 30, \
|
||||
|
@ -157,7 +157,6 @@
|
||||
/* NAND support */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
|
||||
|
@ -95,7 +95,6 @@
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -115,6 +115,5 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#endif
|
||||
|
@ -98,6 +98,5 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#endif
|
||||
|
@ -209,7 +209,6 @@
|
||||
#ifndef CONFIG_NOR_BOOT
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -146,7 +146,6 @@ NANDTGTS \
|
||||
#define CONFIG_SYS_NAND_BASE 0x8000000
|
||||
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -123,7 +123,6 @@
|
||||
#define CONFIG_SYS_BOOTCOUNT_BE
|
||||
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -85,7 +85,6 @@
|
||||
/* Network. */
|
||||
|
||||
/* NAND support */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -23,7 +23,6 @@
|
||||
|
||||
/* NAND support */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
|
@ -188,7 +188,6 @@
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
|
||||
#endif
|
||||
|
@ -97,7 +97,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -121,7 +121,6 @@
|
||||
#undef CONFIG_SYS_NAND_HW_ECC
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
|
||||
|
@ -133,7 +133,6 @@
|
||||
/* Defines for SPL */
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
|
||||
|
@ -80,7 +80,6 @@
|
||||
/* NAND support */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
|
@ -60,8 +60,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
|
||||
|
||||
|
@ -137,7 +137,6 @@
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
# define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
# define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
# define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
# define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
@ -129,7 +129,6 @@
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
@ -52,7 +52,6 @@
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
|
@ -106,7 +106,6 @@
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
|
@ -111,7 +111,6 @@
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
|
@ -114,7 +114,6 @@
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x60000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#endif
|
||||
|
||||
/* OCOTP */
|
||||
|
@ -22,7 +22,6 @@
|
||||
#if defined(CONFIG_MTD_RAW_NAND)
|
||||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
|
@ -27,7 +27,6 @@
|
||||
#if defined(CONFIG_MTD_RAW_NAND)
|
||||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
|
@ -75,7 +75,6 @@
|
||||
#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
|
||||
|
||||
/* NAND config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -18,7 +18,6 @@
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
|
||||
/* NAND devices */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
|
||||
13, 14, 16, 17, 18, 19, 20, 21, 22, \
|
||||
23, 24, 25, 26, 27, 28, 30, 31, 32, \
|
||||
|
@ -122,7 +122,6 @@
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
|
||||
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
|
||||
|
@ -85,7 +85,6 @@
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -85,7 +85,6 @@
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -70,7 +70,6 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
/* Falcon boot support on raw MMC */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */
|
||||
|
@ -82,6 +82,5 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#endif
|
||||
|
@ -46,6 +46,5 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#endif
|
||||
|
@ -46,6 +46,5 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#endif
|
||||
|
@ -73,7 +73,6 @@
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -166,7 +166,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_SIZE (SZ_256M)
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
|
@ -126,7 +126,6 @@
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
|
||||
48, 49, 50, 51, 52, 53, 54, 55,\
|
||||
56, 57, 58, 59, 60, 61, 62, 63}
|
||||
|
@ -168,7 +168,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
|
@ -57,7 +57,6 @@
|
||||
/* NAND: SPL related configs */
|
||||
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -2359,7 +2359,6 @@ CONFIG_SYS_MX7_HCLK
|
||||
CONFIG_SYS_MXS_VDD5V_ONLY
|
||||
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
|
||||
CONFIG_SYS_NAND_4_ADDR_CYCLE
|
||||
CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
CONFIG_SYS_NAND_ACTL_ALE
|
||||
CONFIG_SYS_NAND_ACTL_CLE
|
||||
CONFIG_SYS_NAND_ACTL_DELAY
|
||||
|
Loading…
Reference in New Issue
Block a user