Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
This commit is contained in:
Tom Rini
@@ -69,6 +69,7 @@ int dram_init(void)
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#ifndef CONFIG_SPL_BUILD
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#ifdef CONFIG_XILINX_GPIO
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if (reset_pin != -1)
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gpio_direction_output(reset_pin, 1);
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@@ -77,7 +78,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#ifdef CONFIG_XILINX_TB_WATCHDOG
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hw_watchdog_disable();
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#endif
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#endif
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puts ("Reseting board\n");
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__asm__ __volatile__ (" mts rmsr, r0;" \
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"bra r0");
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@@ -122,40 +123,5 @@ int board_eth_init(bd_t *bis)
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txpp, rxpp);
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#endif
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#ifdef CONFIG_XILINX_LL_TEMAC
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# ifdef XILINX_LLTEMAC_BASEADDR
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# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
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# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
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# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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XILINX_LL_TEMAC_M_SDMA_DCR,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
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# else
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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XILINX_LL_TEMAC_M_SDMA_PLB,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
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# endif
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# endif
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# endif
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# ifdef XILINX_LLTEMAC_BASEADDR1
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# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
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# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
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# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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XILINX_LL_TEMAC_M_SDMA_DCR,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
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# else
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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XILINX_LL_TEMAC_M_SDMA_PLB,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
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# endif
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# endif
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# endif
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#endif
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return ret;
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}
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@@ -56,12 +56,6 @@
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/* Ethernet controller is Ethernet_MAC */
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#define XILINX_EMACLITE_BASEADDR 0x40C00000
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/* LL_TEMAC Ethernet controller */
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#define XILINX_LLTEMAC_BASEADDR 0x44000000
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#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180
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#define XILINX_LLTEMAC_BASEADDR1 0x44200000
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#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000
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/* Watchdog IP is wxi_timebase_wdt_0 */
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#define XILINX_WATCHDOG_BASEADDR 0x50000000
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#define XILINX_WATCHDOG_IRQ 1
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@@ -12,6 +12,7 @@ hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform
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hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform
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hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform
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hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform
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hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform
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# If you want to use customized ps7_init_gpl.c/h,
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# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
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# This line must be placed at the bottom of the list because
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11948
board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
Normal file
11948
board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
Normal file
File diff suppressed because it is too large
Load Diff
97
board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
Normal file
97
board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
Normal file
@@ -0,0 +1,97 @@
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/*
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* Copyright (c) Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*typedef unsigned int u32; */
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/** do we need to make this name more unique ? **/
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/*extern u32 ps7_init_data[]; */
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extern unsigned long *ps7_ddr_init_data;
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extern unsigned long *ps7_mio_init_data;
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extern unsigned long *ps7_pll_init_data;
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extern unsigned long *ps7_clock_init_data;
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extern unsigned long *ps7_peripherals_init_data;
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#define OPCODE_EXIT 0U
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#define OPCODE_CLEAR 1U
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#define OPCODE_WRITE 2U
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#define OPCODE_MASKWRITE 3U
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#define OPCODE_MASKPOLL 4U
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#define OPCODE_MASKDELAY 5U
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#define NEW_PS7_ERR_CODE 1
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/* Encode number of arguments in last nibble */
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#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
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#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
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#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
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#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
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#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
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#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
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/* Returns codes of PS7_Init */
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#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
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#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
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#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
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#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
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#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
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#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
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/* Silicon Versions */
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#define PCW_SILICON_VERSION_1 0
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#define PCW_SILICON_VERSION_2 1
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#define PCW_SILICON_VERSION_3 2
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/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
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#define PS7_POST_CONFIG
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/* Freq of all peripherals */
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#define APU_FREQ 650000000
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#define DDR_FREQ 525000000
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#define DCI_FREQ 10096154
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#define QSPI_FREQ 200000000
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#define SMC_FREQ 10000000
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#define ENET0_FREQ 125000000
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#define ENET1_FREQ 10000000
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#define USB0_FREQ 60000000
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#define USB1_FREQ 60000000
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#define SDIO_FREQ 50000000
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#define UART_FREQ 50000000
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#define SPI_FREQ 10000000
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#define I2C_FREQ 108333336
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#define WDT_FREQ 108333336
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#define TTC_FREQ 50000000
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#define CAN_FREQ 10000000
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#define PCAP_FREQ 200000000
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#define TPIU_FREQ 200000000
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#define FPGA0_FREQ 100000000
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#define FPGA1_FREQ 175000000
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#define FPGA2_FREQ 12264151
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#define FPGA3_FREQ 100000000
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/* For delay calculation using global registers*/
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#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
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#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
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int ps7_config(unsigned long *);
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int ps7_init(void);
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int ps7_post_config(void);
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int ps7_debug(void);
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char *getPS7MessageInfo(unsigned key);
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void perf_start_clock(void);
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void perf_disable_clock(void);
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void perf_reset_clock(void);
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void perf_reset_and_start_timer(void);
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int get_number_of_cycles_for_delay(unsigned int delay);
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#ifdef __cplusplus
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}
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#endif
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