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ARM: AM43xx: EMIF: configure self-refresh entry delay

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Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl
and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the
desired delay in cycles that the EMIF waits without an access to enter
self-refresh, in this case 8192 cycles. With this, code desiring to
enter self refresh only has to toggle one bit to enable it.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach 2014-02-18 07:31:59 -05:00 committed by Tom Rini
parent 3a3939bf3d
commit 4800be4a0c
1 changed files with 2 additions and 2 deletions
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4
arch/arm/cpu/armv7/am33xx/ddr.c
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@ -80,8 +80,8 @@ static void configure_mr(int nr, u32 cs)
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);