powerpc/85xx: Rework P1022 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -17,6 +17,8 @@
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#define SRDS1_MAX_LANES 4
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#define SRDS2_MAX_LANES 2
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static u32 serdes1_prtcl_map, serdes2_prtcl_map;
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static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x00] = {NONE, NONE, NONE, NONE},
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[0x01] = {NONE, NONE, NONE, NONE},
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@ -72,27 +74,41 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret = (1 << device) & serdes1_prtcl_map;
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if (ret)
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return ret;
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return (1 << device) & serdes2_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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unsigned int i;
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int lane;
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debug("%s: dev = %d\n", __FUNCTION__, device);
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debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
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return 0;
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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for (i = 0; i < SRDS1_MAX_LANES; i++) {
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if (serdes1_cfg_tbl[srds_cfg][i] == device)
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return 1;
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if (serdes2_cfg_tbl[srds_cfg][i] == device)
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return 1;
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if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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return 0;
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for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
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serdes2_prtcl_map |= (1 << lane_prtcl);
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}
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}
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@ -30,6 +30,7 @@
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_SYS_HAS_SERDES /* has SERDES */
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#define CONFIG_PHYS_64BIT
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#define CONFIG_ENABLE_36BIT_PHYS
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