Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x
This commit is contained in:
Tom Rini
2020-10-29 11:30:15 -04:00
74 changed files with 2992 additions and 566 deletions

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@@ -8,3 +8,5 @@ Xilinx
xilinx
zynq
zynqmp
zynqmp-r5

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@@ -10,18 +10,28 @@ kernel.
* ata
- Documentation/devicetree/bindings/ata/ahci-ceva.txt
* clock
- Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
* firmware
- Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
* fpga
- Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
* gpio
- Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
- Documentation/devicetree/bindings/gpio/gpio-zynq.txt
* i2c
- Documentation/devicetree/bindings/i2c/i2c-xiic.txt
- Documentation/devicetree/bindings/i2c/i2c-cadence.txt
- Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
- Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
* mmc
- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
- Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
* net
- Documentation/devicetree/bindings/net/macb.txt
- Documentation/devicetree/bindings/net/xilinx_axienet.txt
- Documentation/devicetree/bindings/net/xilinx_emaclite.txt
* nvmem
- Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
* power
- Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
* serial
- Documentation/devicetree/bindings/serial/cdns,uart.txt
- Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt

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@@ -83,7 +83,7 @@ Mainline status
---------------
- Added basic board configurations support.
- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
- Added zynq u-boot bsp code - arch/arm/mach-zynq
- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
- Added zynq drivers:
@@ -99,11 +99,6 @@ Mainline status
- Added basic FDT support for zynq boards
- d-cache support for zynq_gem.c
TODO
----
Add FDT support on individual drivers
* [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
* [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
* [3] http://zedboard.org/product/zedboard

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@@ -0,0 +1,137 @@
.. SPDX-License-Identifier: GPL-2.0
.. (C) Copyright 2020 Xilinx, Inc.
ZYNQMP-R5
=========
About this
----------
This document describes the information about Xilinx Zynq UltraScale+ MPSOC
U-Boot Cortex R5 support.
ZynqMP R5 boards
----------------
* zynqmp-r5 - U-Boot running on RPU Cortex-R5
Building
--------
configure and build armv7 toolchain::
$ make xilinx_zynqmp_r5_defconfig
$ make
Notes
^^^^^
Output fragment is u-boot.
Loading
-------
ZynqMP R5 U-Boot was created for supporting loading OS on RPU. There are two
ways how to start U-Boot on R5.
Bootgen
^^^^^^^
The first way is to use Xilinx FSBL (First stage
bootloader) to load u-boot and start it. The following bif can be used for boot
image generation via Xilinx bootgen utility::
the_ROM_image:
{
[bootloader,destination_cpu=r5-0] fsbl_rpu.elf
[destination_cpu=r5-0]u-boot.elf
}
Bootgen command for building boot.bin::
bootgen -image <bif>.bif -r -w -o i boot.bin
U-Boot cpu command
^^^^^^^^^^^^^^^^^^
The second way to load U-Boot to Cortex R5 is from U-Boot running on A53 as is
visible from the following log::
U-Boot SPL 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
PMUFW: v1.1
Loading new PMUFW cfg obj (2024 bytes)
EL Level: EL3
Multiboot: 0
Trying to boot from MMC2
spl: could not initialize mmc. error: -19
Trying to boot from MMC1
spl_load_image_fat_os: error reading image u-boot.bin, err - -2
NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE: BL31: v2.2(release):v2.2-614-ged9dc512fb9c
NOTICE: BL31: Built : 09:32:09, Mar 13 2020
U-Boot 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
Model: ZynqMP ZCU104 RevC
Board: Xilinx ZynqMP
DRAM: 2 GiB
PMUFW: v1.1
EL Level: EL2
Chip ID: zu7e
WDT: Started with servicing (60s timeout)
NAND: 0 MiB
MMC: mmc@ff170000: 0
Loading Environment from FAT... *** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Bootmode: LVL_SHFT_SD_MODE1
Reset reason: SOFT
Net:
ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id
eth0: ethernet@ff0e0000
Hit any key to stop autoboot: 0
ZynqMP> setenv autoload no
ZynqMP> dhcp
BOOTP broadcast 1
DHCP client bound to address 192.168.0.167 (8 ms)
ZynqMP> tftpboot 20000000 192.168.0.105:u-boot-r5-2.elf
Using ethernet@ff0e0000 device
TFTP from server 192.168.0.105; our IP address is 192.168.0.167
Filename 'u-boot-r5-2.elf'.
Load address: 0x20000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
################
376 KiB/s
done
Bytes transferred = 2075464 (1fab48 hex)
ZynqMP> setenv autostart no
ZynqMP> bootelf -p 20000000
ZynqMP> cpu 4 release 10000000 lockstep
Using TCM jump trampoline for address 0x10000000
R5 lockstep mode
ZynqMP>
Then on second uart you can see U-Boot up and running on R5::
U-Boot 2020.10-rc4-00071-g7045622cc9ba (Sep 16 2020 - 13:38:53 +0200)
Model: Xilinx ZynqMP R5
DRAM: 512 MiB
MMC:
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Net: No ethernet found.
ZynqMP r5>
Please make sure MIO pins for uart are properly configured to see output.

115
doc/board/xilinx/zynqmp.rst Normal file
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@@ -0,0 +1,115 @@
.. SPDX-License-Identifier: GPL-2.0
.. (C) Copyright 2020 Xilinx, Inc.
ZYNQMP
======
About this
----------
This document describes the information about Xilinx Zynq UltraScale+ MPSOC
U-Boot support. Core support is available in arch/arm/mach-zynqmp folder.
ZynqMP boards
-------------
* zcu100 (ultra96 v1), zcu102, zcu104, zcu106 - Evaluation boards
* zc1232 - Characterization boards
* zcu111, zcu208, zcu216 - RFSOC evaluation boards
* zcu1254, zcu1275, zcu1285 - RFSOC characterization boards
* a2197 - System Controller on Versal boards
* mini - Mini U-Boot running out of OCM
* zc1751 - Characterization Processor boards
- zc1751-xm015-dc1
- zc1751-xm016-dc2
- zc1751-xm017-dc3
- zc1751-xm018-dc4
- zc1751-xm019-dc5
Building
--------
Configure and build for zcu102 board::
$ source arm64 toolchain
$ export DEVICE_TREE=zynqmp-zcu102-revA
$ make xilinx_zynqmp_virt_defconfig
$ make
U-Boot SPL flow
---------------
For getting U-Boot SPL flow up and running it is necessary to do some additional
steps because booting device requires external images which are not the part of
U-Boot repository.
PMU firmware
^^^^^^^^^^^^
The Platform Management Unit (PMU) RAM can be loaded with a firmware (PMU
Firmware) at run-time and can be used to extend or customize the functionality
of PMU. The PMU firmware is the part of boot image (boot.bin) and it is
automatically loaded by BootROM. boot.bin can be directly generated by mkimage
tool as the part of make. If you want to create boot.bin with PMU Firmware
include please point CONFIG_PMUFW_INIT_FILE to PMU firmware binary. For example:::
CONFIG_PMUFW_INIT_FILE="<path>/pmu.bin"
If you see below message you need to load PMU Firmware::
PMUFW is not found - Please load it!
The second external blob is PMU Configuration object which is object which is
passed from U-Boot SPL to PMU Firmware for initial system configuration. PMU
configuration object is the part of U-Boot SPL image. For pointing to this
object please use CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE symbol. For example:::
CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE="<path>/pmu_obj.bin"
PMU configuration object
^^^^^^^^^^^^^^^^^^^^^^^^
Object can be obtain in several ways. The easiest way is to take pm_cfg_obj.c
from SDK/Vitis design and build it:::
$ git clone https://github.com/Xilinx/embeddedsw.git
$ export EMBEDDED_SW=$PWD/embeddedsw
$ gcc -c pm_cfg_obj.c -I ${EMBEDDED_SW}/lib/bsp/standalone/src/common/ -I ${EMBEDDED_SW}/lib/sw_services/xilpm/src/zynqmp/client/common/
$ objcopy -O binary pm_cfg_obj.o pmu_obj.bin
The second way is to use tools/zynqmp_pm_cfg_obj_convert.py. For more
information about this tool please run it with -h parameter.
The third way is to extract it from Xilinx FSBL elf file. Object is starting at
XPm_ConfigObject symbol.
Arm Trusted Firmware (ATF)
^^^^^^^^^^^^^^^^^^^^^^^^^^
U-Boot itself can run from EL3 to EL1. Without ATF U-Boot runs in EL3. Boot flow
is U-Boot SPL->U-Boot in EL3. When ATF is used U-Boot normally runs in EL2. Boot
flow is U-Boot SPL->ATF->U-Boot in EL2. As the part of build process u-boot.itb
is generated. When BL31 shell variable is present u-boot.itb is generated with
ATF included. You can point to it by:::
$ export BL31=<path>/bl31.bin
Flashing
--------
SD Card
^^^^^^^
To write an image that boots from a SD card first create a FAT32 partition
and a FAT32 filesystem on the SD card::
sudo fdisk /dev/sdx
sudo mkfs.vfat -F 32 /dev/sdx1
Mount the SD card and copy the SPL and U-Boot to the root directory of the
SD card::
sudo mount -t vfat /dev/sdx1 /mnt
sudo cp spl/boot.bin /mnt
sudo cp u-boot.itb /mnt