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Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Browse Source 
Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x
This commit is contained in:
Tom Rini
2020-10-29 11:30:15 -04:00
parent cdeb7b8f98 908daf86f9
commit 47754334b1
74 changed files with 2992 additions and 566 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/Makefile
View File

@@ -279,6 +279,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \

9
arch/arm/dts/versal-mini-emmc0.dts
View File

@@ -16,10 +16,10 @@
#size-cells = <2>;
model = "Xilinx Versal MINI eMMC0";
clk25: clk25 {
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <25000000>;
clock-frequency = <200000000>;
};
dcc: dcc {
@@ -38,9 +38,12 @@
sdhci0: sdhci@f1040000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
status = "okay";
non-removable;
disable-wp;
bus-width = <8>;
reg = <0x0 0xf1040000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk25 &clk25>;
clocks = <&clk200 &clk200>;
xlnx,device_id = <0>;
no-1-8-v;
xlnx,mio-bank = <0>;

9
arch/arm/dts/versal-mini-emmc1.dts
View File

@@ -16,10 +16,10 @@
#size-cells = <2>;
model = "Xilinx Versal MINI eMMC1";
clk25: clk25 {
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <25000000>;
clock-frequency = <200000000>;
};
dcc: dcc {
@@ -38,9 +38,12 @@
sdhci1: sdhci@f1050000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
status = "okay";
non-removable;
disable-wp;
bus-width = <8>;
reg = <0x0 0xf1050000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk25 &clk25>;
clocks = <&clk200 &clk200>;
xlnx,device_id = <1>;
no-1-8-v;
xlnx,mio-bank = <0>;

120
arch/arm/dts/zynq-zturn-common.dtsi Normal file
View File

@@ -0,0 +1,120 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
* Copyright (C) 2017 Alexander Graf <agraf@suse.de>
*
* Based on zynq-zed.dts which is:
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
mmc0 = &sdhci0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
usr-led1 {
label = "usr-led1";
gpios = <&gpio0 0x0 0x1>;
default-state = "off";
};
usr-led2 {
label = "usr-led2";
gpios = <&gpio0 0x9 0x1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
K1 {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
wakeup-source;
autorepeat;
};
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
stlm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;
};
};

15
arch/arm/dts/zynq-zturn-v5.dts Normal file
View File

@@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "zynq-zturn-common.dtsi"
/ {
model = "Zynq Z-Turn MYIR Board V5";
compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
};
&gem0 {
ethernet_phy: ethernet-phy@0 {
reg = <0x3>;
};
};

109
arch/arm/dts/zynq-zturn.dts
View File

@@ -1,122 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
* Copyright (C) 2017 Alexander Graf <agraf@suse.de>
*
* Based on zynq-zed.dts which is:
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "zynq-zturn-common.dtsi"
/ {
model = "Zynq Z-Turn MYIR Board";
compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
mmc0 = &sdhci0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
usr-led1 {
label = "usr-led1";
gpios = <&gpio0 0x0 0x1>;
default-state = "off";
};
usr-led2 {
label = "usr-led2";
gpios = <&gpio0 0x9 0x1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
K1 {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
wakeup-source;
autorepeat;
};
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0x0>;
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
stlm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;
};
};

2
arch/arm/dts/zynqmp-mini-qspi.dts
View File

@@ -70,7 +70,7 @@
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
spi-max-frequency = <40000000>;
};
};

14
arch/arm/mach-zynq/spl.c
View File

@@ -9,7 +9,6 @@
#include <init.h>
#include <log.h>
#include <spl.h>
#include <generated/dt.h>
#include <asm/io.h>
#include <asm/spl.h>
@@ -86,16 +85,3 @@ void spl_board_prepare_for_boot(void)
ps7_post_config();
debug("SPL bye\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE);
if (!strcmp(name, DEVICE_TREE))
return 0;
return -1;
}
#endif

10
arch/arm/mach-zynqmp/include/mach/sys_proto.h
View File

@@ -9,6 +9,16 @@
#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
#define KEY_PTR_LEN 32
#define IV_SIZE 12
#define RSA_KEY_SIZE 512
#define MODULUS_LEN 512
#define PRIV_EXPO_LEN 512
#define PUB_EXPO_LEN 4
#define ZYNQMP_SHA3_INIT 1
#define ZYNQMP_SHA3_UPDATE 2
#define ZYNQMP_SHA3_FINAL 4
#define ZYNQMP_SHA3_SIZE 48
#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
#define ZYNQMP_FPGA_BIT_AUTH_OCM 2

10
arch/arm/mach-zynqmp/spl.c
View File

@@ -119,13 +119,3 @@ int spl_start_uboot(void)
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return -1;
}
#endif