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sunxi: mmc: Fix phase delays

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U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where
PLL5 is used, with clock rates respectively 600MHz and 768MHz.
Thus there are different phase degree steps - 24 for the kernel and
30 for u-boot.

In the kernel driver the phase is set 90 deg for output and 120 for
sample. Dividing by 30 will result values 3 and 4. Those are the
values set in the u-boot driver.

However, the condition defining delays is wrong. MMC core driver
requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but
phase is set 30 deg for output and 120 deg for sample.

Apparently this works for most cards.
On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains
about it. Maybe there is other boards with similar problem?
So the fix is to match delays for both u-boot and kernel.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Stefan Mavrodiev 2018-03-27 16:57:23 +03:00 committed by Jagan Teki
parent 275d80a4c2
commit 4744d81cc0
1 changed files with 4 additions and 4 deletions
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8
drivers/mmc/sunxi_mmc.c
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@ -147,19 +147,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
oclk_dly = 0; oclk_dly = 0;
sclk_dly = 5; sclk_dly = 5;
#ifdef CONFIG_MACH_SUN9I #ifdef CONFIG_MACH_SUN9I
} else if (hz <= 50000000) { } else if (hz <= 52000000) {
oclk_dly = 5; oclk_dly = 5;
sclk_dly = 4; sclk_dly = 4;
} else { } else {
/* hz > 50000000 */ /* hz > 52000000 */
oclk_dly = 2; oclk_dly = 2;
sclk_dly = 4; sclk_dly = 4;
#else #else
} else if (hz <= 50000000) { } else if (hz <= 52000000) {
oclk_dly = 3; oclk_dly = 3;
sclk_dly = 4; sclk_dly = 4;
} else { } else {
/* hz > 50000000 */ /* hz > 52000000 */
oclk_dly = 1; oclk_dly = 1;
sclk_dly = 4; sclk_dly = 4;
#endif #endif