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Merge git://www.denx.de/git/u-boot-imx

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Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2017-08-16 18:07:20 -04:00
parent 390194d43f e872f27a02
commit 470135be27
19 changed files with 1069 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/Kconfig
View File

@@ -97,6 +97,9 @@ config ARM_ERRATA_833069
config ARM_ERRATA_833471
bool
config ARM_ERRATA_845369
bool
config ARM_ERRATA_852421
bool

6
arch/arm/cpu/armv7/start.S
View File

@@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_845369
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 22 @ set bit #22
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20 @ get variant field

8
arch/arm/include/asm/arch-mx6/mx6q_pins.h
View File

@@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0)
MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0)
MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0)
MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0)
@@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0)
MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0)
MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0)
MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0)
MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0)
@@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0)
MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0)
MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0)
@@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0)
MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0)
MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0)
MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0)
MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0)
MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0)
MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0)
MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0)

22
arch/arm/mach-imx/mx6/Kconfig
View File

@@ -1,24 +1,32 @@
if ARCH_MX6
config MX6_SMP
select ARM_ERRATA_751472
select ARM_ERRATA_761320
select ARM_ERRATA_794072
select ARM_ERRATA_845369
bool
config MX6
select ARM_ERRATA_743622 if !MX6UL
bool
default y
select ARM_ERRATA_743622 if !MX6UL
select ARM_ERRATA_751472 if !MX6UL
select ARM_ERRATA_761320 if !MX6UL
select ARM_ERRATA_794072 if !MX6UL
imply CMD_FUSE
config MX6D
select MX6_SMP
bool
config MX6DL
select MX6_SMP
bool
config MX6Q
select MX6_SMP
bool
config MX6QDL
select MX6_SMP
bool
config MX6S
@@ -331,6 +339,11 @@ config TARGET_PCM058
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_SECOMX6
bool "secomx6 boards"
@@ -428,6 +441,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pfla02/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"

2
arch/arm/mach-imx/mx6/clock.c
View File

@@ -19,7 +19,7 @@ enum pll_clocks {
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
PLL_AUDIO, /* AUDIO PLL */
PLL_VIDEO, /* AUDIO PLL */
PLL_VIDEO, /* VIDEO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

55
arch/arm/mach-imx/mx6/soc.c
View File

@@ -114,6 +114,12 @@ u32 get_cpu_rev(void)
#define OCOTP_CFG3_SPEED_528MHZ 1
#define OCOTP_CFG3_SPEED_696MHZ 2
/*
* For i.MX6ULL
*/
#define OCOTP_CFG3_SPEED_792MHZ 2
#define OCOTP_CFG3_SPEED_900MHZ 3
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -126,11 +132,22 @@ u32 get_cpu_speed_grade_hz(void)
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
if (is_mx6ul() || is_mx6ull()) {
if (is_mx6ul()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
return 69600000;
return 696000000;
else
return 0;
}
if (is_mx6ull()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_792MHZ)
return 792000000;
else if (val == OCOTP_CFG3_SPEED_900MHZ)
return 900000000;
else
return 0;
}
@@ -234,6 +251,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
u32 val, step, old, reg = readl(&anatop->reg_core);
u8 shift;
/* No LDO_SOC/PU/ARM */
if (is_mx6sll())
return 0;
if (mv < 725)
val = 0x00; /* Power gated off */
else if (mv > 1450)
@@ -293,7 +314,7 @@ static void clear_mmdc_ch_mask(void)
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -344,20 +365,10 @@ static void init_bandgap(void)
}
}
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg;
reg = readl(&mxc_ccm->cscmr1);
reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
writel(reg, &mxc_ccm->cscmr1);
}
#endif
int arch_cpu_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
init_aips();
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
@@ -421,12 +432,14 @@ int arch_cpu_init(void)
}
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();
#endif
if (is_mx6sl())
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
if (is_mx6sx())
setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
init_src();
return 0;
@@ -495,6 +508,10 @@ uint mmc_get_env_part(struct mmc *mmc)
int board_postclk_init(void)
{
/* NO LDO SOC on i.MX6SLL */
if (is_mx6sll())
return 0;
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
return 0;
@@ -576,7 +593,7 @@ void s_init(void)
u32 mask528;
u32 reg, periph1, periph2;
if (is_mx6sx() || is_mx6ul() || is_mx6ull())
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

7
arch/arm/mach-imx/mx7/soc.c
View File

@@ -31,7 +31,7 @@ U_BOOT_DEVICE(imx7_thermal) = {
};
#endif
#ifdef CONFIG_IMX_RDC
#if CONFIG_IS_ENABLED(IMX_RDC)
/*
* In current design, if any peripheral was assigned to both A7 and M4,
* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
@@ -245,8 +245,9 @@ int arch_cpu_init(void)
mxs_dma_init();
#endif
if (IS_ENABLED(CONFIG_IMX_RDC))
isolate_resource();
#if CONFIG_IS_ENABLED(IMX_RDC)
isolate_resource();
#endif
return 0;
}