powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Liu Gang
Andy Fleming
parent
b5f7c8732a
commit
461632bd71
@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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/*
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* SRIOBOOT-SLAVE. When slave boot, the address of the
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* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
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* space is at 0xfff00000, it covered the 0xfffff000.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
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CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
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CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#else
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@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 16, BOOKE_PAGESZ_1M, 1),
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#endif
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/*
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* SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
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* and ENV from master
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* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
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* fetching ucode and ENV from master
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
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CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
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CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 17, BOOKE_PAGESZ_1M, 1),
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#endif
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@ -787,13 +787,13 @@ P2041RDB_NAND powerpc mpc85xx p2041rdb freescale
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P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT
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P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P2041RDB_SRIOBOOT_SLAVE powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P2041RDB_SRIO_PCIE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P3041DS powerpc mpc85xx corenet_ds freescale
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P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
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P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P3041DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P3060QDS powerpc mpc85xx p3060qds freescale
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P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT
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@ -801,13 +801,13 @@ P4080DS powerpc mpc85xx corenet_ds freesca
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P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
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P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P4080DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P5020DS powerpc mpc85xx corenet_ds freescale
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P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
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P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
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stxgp3 powerpc mpc85xx stxgp3 stx
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stxssa powerpc mpc85xx stxssa stx - stxssa
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@ -62,8 +62,8 @@ int env_init(void)
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#ifdef CONFIG_CMD_SAVEENV
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int saveenv(void)
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{
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#ifdef CONFIG_SRIOBOOT_SLAVE
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printf("Can not support the 'saveenv' when boot from SRIO!\n");
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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printf("Can not support the 'saveenv' when boot from SRIO or PCIE!\n");
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return 1;
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#else
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return 0;
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@ -275,25 +275,52 @@ void init_laws(void)
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law_table[i].size, law_table[i].trgt_id);
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}
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* check RCW to get which port is used for boot */
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 bootloc = in_be32(&gur->rcwsr[6]);
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/* in SRIO boot we need to set specail LAWs for SRIO interfaces */
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/*
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* in SRIO or PCIE boot we need to set specail LAWs for
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* SRIO or PCIE interfaces.
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*/
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switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
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case 0x0: /* boot from PCIE1 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_1);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_1);
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break;
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case 0x1: /* boot from PCIE2 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_2);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_2);
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break;
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case 0x2: /* boot from PCIE3 */
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_3);
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_PCIE_3);
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break;
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case 0x8: /* boot from SRIO1 */
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set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_1);
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set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_1);
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break;
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case 0x9: /* boot from SRIO2 */
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set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_2);
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set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
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set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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LAW_SIZE_1M,
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LAW_TRGT_IF_RIO_2);
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break;
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@ -36,11 +36,11 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* Set 1M boot space */
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#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_NO_FLASH
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#endif
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@ -82,7 +82,7 @@
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#define CONFIG_ENV_OVERWRITE
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#ifdef CONFIG_SYS_NO_FLASH
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#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIOBOOT_SLAVE)
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#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define CONFIG_ENV_IS_NOWHERE
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#endif
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#else
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@ -113,7 +113,7 @@
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define CONFIG_ENV_IS_IN_REMOTE
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#define CONFIG_ENV_ADDR 0xffe20000
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#define CONFIG_ENV_SIZE 0x2000
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@ -407,12 +407,12 @@ unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
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/*
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* SRIOBOOT - SLAVE
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* SRIO_PCIE_BOOT - SLAVE
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*/
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
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#endif
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/*
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@ -527,13 +527,13 @@ unsigned long get_board_sys_clk(unsigned long dummy);
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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/*
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* Slave has no ucode locally, it can fetch this from remote. When implementing
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* in two corenet boards, slave's ucode could be stored in master's memory
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* space, the address can be mapped from slave TLB->slave LAW->
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* slave SRIO outbound window->master inbound window->master LAW->
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* the ucode address in master's NOR flash.
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* slave SRIO or PCIE outbound window->master inbound window->
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* master LAW->the ucode address in master's memory space.
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*/
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#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
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#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
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@ -33,11 +33,11 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* Set 1M boot space */
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#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_NO_FLASH
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#endif
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@ -77,7 +77,7 @@
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#define CONFIG_ENV_OVERWRITE
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#ifdef CONFIG_SYS_NO_FLASH
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#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
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#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
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#define CONFIG_ENV_IS_NOWHERE
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#endif
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#else
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@ -108,7 +108,7 @@
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define CONFIG_ENV_IS_IN_REMOTE
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#define CONFIG_ENV_ADDR 0xffe20000
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#define CONFIG_ENV_SIZE 0x2000
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@ -409,12 +409,12 @@
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#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
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/*
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* SRIOBOOT - SLAVE
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* SRIO_PCIE_BOOT - SLAVE
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*/
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
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#endif
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/*
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@ -537,13 +537,13 @@
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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/*
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* Slave has no ucode locally, it can fetch this from remote. When implementing
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* in two corenet boards, slave's ucode could be stored in master's memory
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* space, the address can be mapped from slave TLB->slave LAW->
|
||||
* slave SRIO outbound window->master inbound window->master LAW->
|
||||
* the ucode address in master's NOR flash.
|
||||
* slave SRIO or PCIE outbound window->master inbound window->
|
||||
* master LAW->the ucode address in master's memory space.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user