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Merge tag 'arc-updates-for-2018.11-rc2' of git://git.denx.de/u-boot-arc

Browse Source 
Here we do a couple of impovements for all ARC boards
as well as introduce yet another developemnt board.

1. Now for ARC boards we print CPU and board info
   which is useful for users and helps with
   analysis of logs "post-mortem".

2. Synopsys IoT development kit support is added
   This one might bw a bit too late as we're past RC1
   but:
    1) This doesn't affect any other arches etc
       as we change purely ARC code.
    2) I've got a chance to talk about U-Boot on
       IoT platforms during ELCE (my proposal was on
       a wait list and only this week I've got
       an update and invitation to talk) so it would
       be good to have this board as a primer in upstream
       code-base by the time of ELCE 2018.
    3) For complete support of IoT devkit I'm yet to
       significantly rework regmap subsystem in U-Boot
       but that's a different topic and hopefully it will
       be done sometime soon... though not this release
       cycle for sure.
This commit is contained in:
Tom Rini 2018-10-05 10:16:31 -04:00
commit 46031b3aa0
20 changed files with 492 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arc/Kconfig
View File

@ -157,6 +157,10 @@ config TARGET_EMDK
config TARGET_HSDK
bool "Support Synpsys HS DevelopmentKit board"
config TARGET_IOT_DEVKIT
bool "Synopsys Brite IoT Development kit"
select CPU_ARCEM6
endchoice
source "board/abilis/tb100/Kconfig"
@ -164,5 +168,6 @@ source "board/synopsys/Kconfig"
source "board/synopsys/axs10x/Kconfig"
source "board/synopsys/emdk/Kconfig"
source "board/synopsys/hsdk/Kconfig"
source "board/synopsys/iot_devkit/Kconfig"
endmenu

6
arch/arc/config.mk
View File

@ -9,21 +9,15 @@ CONFIG_SYS_BIG_ENDIAN = 1
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
ARC_CROSS_COMPILE := arc-linux-
PLATFORM_LDFLAGS += -EL
PLATFORM_CPPFLAGS += -mlittle-endian
endif
ifdef CONFIG_SYS_BIG_ENDIAN
ARC_CROSS_COMPILE := arceb-linux-
PLATFORM_LDFLAGS += -EB
PLATFORM_CPPFLAGS += -mbig-endian
endif
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := $(ARC_CROSS_COMPILE)
endif
ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif

1
arch/arc/dts/Makefile
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@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
dtb-$(CONFIG_TARGET_EMDK) += emdk.dtb
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
targets += $(dtb-y)

2
arch/arc/dts/abilis_tb100.dts
View File

@ -7,6 +7,8 @@
#include "skeleton.dtsi"
/ {
model = "abilis,tb100";
aliases {
console = &uart0;
};

2
arch/arc/dts/axs101.dts
View File

@ -9,6 +9,8 @@
/ {
model = "snps,axs101";
chosen {
stdout-path = &uart0;
};

2
arch/arc/dts/axs103.dts
View File

@ -9,6 +9,8 @@
/ {
model = "snps,axs103";
chosen {
stdout-path = &uart0;
};

2
arch/arc/dts/emdk.dts
View File

@ -7,6 +7,8 @@
#include "skeleton.dtsi"
/ {
model = "snps,emdk";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arc/dts/hsdk.dts
View File

@ -8,6 +8,8 @@
#include "dt-bindings/clock/snps,hsdk-cgu.h"
/ {
model = "snps,hsdk";
#address-cells = <1>;
#size-cells = <1>;

45
arch/arc/dts/iot_devkit.dts Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
/dts-v1/;
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
};
cpu_card {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <144000000>;
u-boot,dm-pre-reloc;
};
};
uart0: serial0@80014000 {
compatible = "snps,dw-apb-uart";
clock-frequency = <16000000>;
reg = <0x80014000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
};
usb: usb@f0040000 {
compatible = "snps,dwc2";
reg = <0xf0040000 0x10000>;
phys = <&usbphy>;
phy-names = "usb2-phy";
};
usbphy: phy {
compatible = "nop-phy";
#phy-cells = <0>;
};
};

2
arch/arc/dts/nsim.dts
View File

@ -7,6 +7,8 @@
#include "skeleton.dtsi"
/ {
model = "snps,nsim";
aliases {
console = &arcuart0;
};

35
arch/arc/lib/cpu.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
@ -33,3 +33,36 @@ int dram_init(void)
{
return 0;
}
#ifdef CONFIG_DISPLAY_CPUINFO
const char *decode_identity(void)
{
int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
switch (arcver) {
/* ARCompact cores */
case 0x32: return "ARC 700 v4.4-4.5";
case 0x33: return "ARC 700 v4.6-v4.9";
case 0x34: return "ARC 700 v4.10";
case 0x35: return "ARC 700 v4.11";
/* ARCv2 cores */
case 0x41: return "ARC EM v1.1a";
case 0x42: return "ARC EM v3.0";
case 0x43: return "ARC EM v4.0";
case 0x50: return "ARC HS v1.0";
case 0x51: return "ARC EM v2.0";
case 0x52: return "ARC EM v2.1";
case 0x53: return "ARC HS v3.0";
case 0x54: return "ARC HS v4.0";
default: return "Unknown ARC core";
}
}
int print_cpuinfo(void)
{
printf("CPU: %s\n", decode_identity());
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

12
board/synopsys/iot_devkit/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_IOT_DEVKIT
config SYS_BOARD
default "iot_devkit"
config SYS_VENDOR
default "synopsys"
config SYS_CONFIG_NAME
default "iot_devkit"
endif

5
board/synopsys/iot_devkit/MAINTAINERS Normal file
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@ -0,0 +1,5 @@
IOT DEVKIT BOARD
M: Alexey Brodkin <abrodkin@synopsys.com>
S: Maintained
F: board/synopsys/iot_devkit/
F: configs/iot_devkit_defconfig

7
board/synopsys/iot_devkit/Makefile Normal file
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@ -0,0 +1,7 @@
#
# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += iot_devkit.o

2
board/synopsys/iot_devkit/config.mk Normal file
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@ -0,0 +1,2 @@
PLATFORM_CPPFLAGS += -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter
LDSCRIPT = $(srctree)/board/synopsys/iot_devkit/u-boot.lds

168
board/synopsys/iot_devkit/iot_devkit.c Normal file
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@ -0,0 +1,168 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <malloc.h>
#include <dwmmc.h>
#include <linux/libfdt.h>
#include <fdtdec.h>
#include <asm/arcregs.h>
DECLARE_GLOBAL_DATA_PTR;
#define SYSCON_BASE 0xf000a000
#define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
#define APBCKDIV (void *)(SYSCON_BASE + 0x08)
#define APBCKEN (void *)(SYSCON_BASE + 0x0C)
#define CLKSEL (void *)(SYSCON_BASE + 0x24)
#define CLKSTAT (void *)(SYSCON_BASE + 0x28)
#define PLLCON (void *)(SYSCON_BASE + 0x2C)
#define APBCKSEL (void *)(SYSCON_BASE + 0x30)
#define AHBCKEN (void *)(SYSCON_BASE + 0x34)
#define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
#define USBCFG (void *)(SYSCON_BASE + 0x7c)
#define PLL_MASK_0 0xffcfffff
#define PLL_MASK_1 0xffcfff00
#define PLL_MASK_2 0xfbcfff00
#define CLKSEL_DEFAULT 0x5a690000
static int set_cpu_freq(unsigned int clk)
{
clk /= 1000000;
/* Set clk to ext Xtal (LSN value 0) */
writel(CLKSEL_DEFAULT, CLKSEL);
switch (clk) {
case 16:
/* Bypass mode */
return 0;
case 50:
writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
/* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
/* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
break;
case 72:
writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
/* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
/* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
break;
case 100:
writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
/* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
/* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
break;
case 144:
writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
/* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
/* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
break;
default:
return -EINVAL;
}
while (!(readl(CLKSTAT) & 0x4))
;
/* Set clk from PLL on bus (LSN = 1) */
writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
return 0;
}
extern u8 __rom_end[];
extern u8 __ram_start[];
extern u8 __ram_end[];
/*
* Use mach_cpu_init() for .data section copy as board_early_init_f() will be
* too late: initf_dm() will use a value of "av_" variable from not yet
* initialized (by copy) area.
*/
int mach_cpu_init(void)
{
int offset, freq;
/* Don't relocate U-Boot */
gd->flags |= GD_FLG_SKIP_RELOC;
/* Copy data from ROM to RAM */
u8 *src = __rom_end;
u8 *dst = __ram_start;
while (dst < __ram_end)
*dst++ = *src++;
/* Enable debug uart */
#define DEBUG_UART_BASE 0x80014000
#define DEBUG_UART_DLF_OFFSET 0xc0
write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
if (offset < 0)
return offset;
freq = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
if (!freq)
return -EINVAL;
/* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
if (freq > 100000000) {
u32 reg = readl(AHBCKDIV);
reg &= ~(0xF << 8);
reg |= 2 << 8;
writel(reg, AHBCKDIV);
}
return set_cpu_freq(freq);
}
#define ARC_PERIPHERAL_BASE 0xF0000000
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xB000)
int board_mmc_init(bd_t *bis)
{
struct dwmci_host *host = NULL;
host = malloc(sizeof(struct dwmci_host));
if (!host) {
printf("dwmci_host malloc fail!\n");
return -ENOMEM;
}
memset(host, 0, sizeof(struct dwmci_host));
host->name = "Synopsys Mobile storage";
host->ioaddr = (void *)SDIO_BASE;
host->buswidth = 4;
host->dev_index = 0;
host->bus_hz = 50000000;
add_dwmci(host, host->bus_hz / 2, 400000);
return 0;
}
int checkboard(void)
{
puts("Board: Synopsys IoT Development Kit\n");
return 0;
};

77
board/synopsys/iot_devkit/u-boot.lds Normal file
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@ -0,0 +1,77 @@
/*
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
MEMORY {
ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
RAM : ORIGIN = RAM_DATA_BASE, LENGTH = RAM_DATA_SIZE
}
OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
OUTPUT_ARCH(arc)
ENTRY(_start)
SECTIONS
{
. = CONFIG_SYS_MONITOR_BASE;
__image_copy_start = .;
.ivt :
{
__ivt_start = .;
KEEP(*(.ivt));
__ivt_end = .;
} > ROM
. = ALIGN(1024);
.text : {
__text_start = .;
arch/arc/lib/start.o (.text*)
*(.text*)
__text_end = .;
} > ROM
. = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} > ROM
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
/* Mark RAM's LMA */
. = ALIGN(4);
__rom_end = .;
} > ROM
.data : {
/* Mark RAM's VMA */
. = ALIGN(4);
/*
* Everything between __ram_start and __ram_start will be
* copied from ROM to RAM in board_early_init_f().
*/
__ram_start = .;
*(.data*)
__ram_end = .;
} > RAM AT > ROM
.bss : {
. = ALIGN(1024);
__bss_start = .;
*(.bss*)
__bss_end = .;
} > RAM
/* Keep relocation-related symbols to make linker happy */
__rel_dyn_start = .;
__rel_dyn_end = .;
__image_copy_end = .;
__init_end = .;
}

4
common/Kconfig
View File

@ -573,7 +573,7 @@ config BOARD_LATE_INIT
config DISPLAY_CPUINFO
bool "Display information about the CPU during start up"
default y if ARM || NIOS2 || X86 || XTENSA || M68K
default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K
help
Display information about the CPU that U-Boot is running on
when U-Boot starts up. The function print_cpuinfo() is called
@ -581,7 +581,7 @@ config DISPLAY_CPUINFO
config DISPLAY_BOARDINFO
bool "Display information about the board during early start up"
default y if ARM || M68K || MIPS || PPC || SANDBOX || XTENSA
default y if ARC || ARM || M68K || MIPS || PPC || SANDBOX || XTENSA
help
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called

38
configs/iot_devkit_defconfig Normal file
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@ -0,0 +1,38 @@
CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
CONFIG_CPU_ARCEM6=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_IOT_DEVKIT=y
CONFIG_SYS_TEXT_BASE=0x20000000
CONFIG_SYS_CLK_FREQ=16000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_PROMPT="IoTDK# "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="iot_devkit"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_DM=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC2_BUFFER_SIZE=16
CONFIG_USB_STORAGE=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=4096

84
include/configs/iot_devkit.h Normal file
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@ -0,0 +1,84 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
#ifndef _CONFIG_IOT_DEVKIT_H_
#define _CONFIG_IOT_DEVKIT_H_
#include <linux/sizes.h>
/*
* MEMORY MAP
*
* eFlash: 0x0000_0000 - 0x0008_0000 (512K)
* ICCM: 0x2000_0000 - 0x2004_0000 (256K)
* SRAM: 0x3000_0000 - 0x3002_0000 (128K)
* DCCM: 0x8000_0000 - 0x8002_0000 (128K)
* Note: only data goes here, as IFQ cannot fetch instructions from DCCM
*
*
* RAM PARTITIONING
*
* +-----------+----------+---------------------+-------------+
* | <-- Stack | .data | Malloc | Environment |
* +-----------+----------+---------------------+-------------+
* : : : :\___________/
* : : : : |
* : : : : CONFIG_ENV_SIZE
* : : \____________________/
* : : |
* : : CONFIG_SYS_MALLOC_LEN
* : :
* : Specified explicitly by CONFIG_SYS_INIT_SP_ADDR
* :
* Specified explicitly by CONFIG_SYS_SDRAM_BASE
*
* NOTES:
* - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down,
* i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing
* that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on
* stack any longer and values popped from stack will contain garbage
* leading to unexpected behavior, typically but not limited to:
* - "Returning" back to bogus caller function
* - Reading data from weird addresses
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define SRAM_BASE 0x30000000
#define SRAM_SIZE SZ_128K
#define DCCM_BASE 0x80000000
#define DCCM_SIZE SZ_128K
#define CONFIG_SYS_SDRAM_BASE DCCM_BASE
#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
#define CONFIG_SYS_MALLOC_LEN SZ_64K
#define CONFIG_SYS_BOOTM_LEN SZ_128K
#define CONFIG_SYS_LOAD_ADDR SRAM_BASE
#define ROM_BASE CONFIG_SYS_MONITOR_BASE
#define ROM_SIZE SZ_256K
#define RAM_DATA_BASE CONFIG_SYS_INIT_SP_ADDR
#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \
(CONFIG_SYS_INIT_SP_ADDR - \
CONFIG_SYS_SDRAM_BASE) - \
CONFIG_SYS_MALLOC_LEN - \
CONFIG_ENV_SIZE
/* Required by DW MMC driver */
#define CONFIG_BOUNCE_BUFFER
/*
* Environment
*/
#define CONFIG_ENV_SIZE SZ_4K
#define CONFIG_BOOTFILE "app.bin"
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#endif /* _CONFIG_IOT_DEVKIT_H_ */