stm32mp1: add syscfg initialization
Initialize the system configuration for basic boot - update interconnect setting - disable pull-down for boot pin - enable High Speed Low Voltage Pad mode for SPI, SDMMC, ETH, QSPI - activate I/O compensation Done by SSBL = TF-A for trusted boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay
parent
6c09eb9e7e
commit
45459747ca
@ -11,13 +11,47 @@
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#include <misc.h>
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#include <phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/arch/stm32.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/stm32.h>
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#include <power/regulator.h>
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#include <usb/dwc2_udc.h>
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/* SYSCFG registers */
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#define SYSCFG_BOOTR 0x00
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#define SYSCFG_PMCSETR 0x04
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#define SYSCFG_IOCTRLSETR 0x18
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#define SYSCFG_ICNR 0x1C
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#define SYSCFG_CMPCR 0x20
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#define SYSCFG_CMPENSETR 0x24
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#define SYSCFG_PMCCLRR 0x44
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
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#define SYSCFG_CMPCR_SW_CTRL BIT(1)
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#define SYSCFG_CMPCR_READY BIT(8)
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
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#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
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#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
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#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21)
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#define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21)
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#define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21)
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/*
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* Get a global data pointer
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*/
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@ -270,6 +304,98 @@ int board_usb_cleanup(int index, enum usb_init_type init)
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return 0;
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}
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static void sysconf_init(void)
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{
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#ifndef CONFIG_STM32MP1_TRUSTED
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u8 *syscfg;
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *pwr_dev;
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struct udevice *pwr_reg;
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struct udevice *dev;
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int ret;
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u32 otp = 0;
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#endif
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u32 bootr;
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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/* interconnect update : select master using the port 1 */
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/* LTDC = AXI_M9 */
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/* GPU = AXI_M8 */
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/* today information is hardcoded in U-Boot */
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writel(BIT(9), syscfg + SYSCFG_ICNR);
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/* disable Pull-Down for boot pin connected to VDD */
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bootr = readl(syscfg + SYSCFG_BOOTR);
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bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
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bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
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writel(bootr, syscfg + SYSCFG_BOOTR);
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#ifdef CONFIG_DM_REGULATOR
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/* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
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* The customer will have to disable this for low frequencies
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* or if AFMUX is selected but the function not used, typically for
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* TRACE. Otherwise, impact on power consumption.
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*
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* WARNING:
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* enabling High Speed mode while VDD>2.7V
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* with the OTP product_below_2v5 (OTP 18, BIT 13)
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* erroneously set to 1 can damage the IC!
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* => U-Boot set the register only if VDD < 2.7V (in DT)
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* but this value need to be consistent with board design
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*/
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ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev);
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if (!ret) {
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stm32mp_bsec),
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&dev);
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if (ret) {
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pr_err("Can't find stm32mp_bsec driver\n");
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return;
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}
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ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
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if (!ret)
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otp = otp & BIT(13);
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/* get VDD = pwr-supply */
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ret = device_get_supply_regulator(pwr_dev, "pwr-supply",
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&pwr_reg);
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/* check if VDD is Low Voltage */
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if (!ret) {
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if (regulator_get_value(pwr_reg) < 2700000) {
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writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
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SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
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SYSCFG_IOCTRLSETR_HSLVEN_ETH |
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SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
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SYSCFG_IOCTRLSETR_HSLVEN_SPI,
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syscfg + SYSCFG_IOCTRLSETR);
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if (!otp)
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pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
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} else {
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if (otp)
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pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
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}
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} else {
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debug("VDD unknown");
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}
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}
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#endif
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/* activate automatic I/O compensation
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* warning: need to ensure CSI enabled and ready in clock driver
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*/
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writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
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while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
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;
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clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
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#endif
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}
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/* board dependent setup after realloc */
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int board_init(void)
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{
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@ -278,6 +404,8 @@ int board_init(void)
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board_key_check();
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sysconf_init();
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if (IS_ENABLED(CONFIG_LED))
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led_default_state();
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