powerpc/p2041rdb: set sysclk according to status of physical switch SW1
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -30,6 +30,7 @@ typedef struct cpld_data {
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u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
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u8 sw[1]; /* 0xd - SW2 Status */
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u8 system_rst_default; /* 0xe - system reset to default register */
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u8 sysclk_sw1; /* 0xf - sysclk configuration register */
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} __attribute__ ((packed)) cpld_data_t;
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#define SERDES_MUX_LANE_6_MASK 0x2
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@ -41,6 +42,8 @@ typedef struct cpld_data {
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#define SERDES_MUX_LANE_D_MASK 0x8
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#define SERDES_MUX_LANE_D_SHIFT 3
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#define CPLD_SWITCH_BANK_ENABLE 0x40
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#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
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#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */
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/* Pointer to the CPLD register set */
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#define cpld ((cpld_data_t *)CPLD_BASE)
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@ -130,6 +130,20 @@ int board_early_init_r(void)
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return 0;
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}
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unsigned long get_board_sys_clk(unsigned long dummy)
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{
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u8 sysclk_conf = CPLD_READ(sysclk_sw1);
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switch (sysclk_conf & 0x7) {
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case CPLD_SYSCLK_83:
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return 83333333;
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case CPLD_SYSCLK_100:
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return 100000000;
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default:
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return 66666666;
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}
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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@ -102,7 +102,10 @@
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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#define CONFIG_SYS_CLK_FREQ 66666666
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
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/*
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* These can be toggled for performance analysis, otherwise use default.
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