powerpc: Remove configs/C29XPCIE_NAND_defconfig board
DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Patch-cc: Po Liu <po.liu@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Jagan Teki
parent
55bcea4fb4
commit
447ec175b2
@ -24,15 +24,6 @@ config TARGET_SOCRATES
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bool "Support socrates"
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select ARCH_MPC8544
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config TARGET_C29XPCIE
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bool "Support C29XPCIE"
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select ARCH_C29X
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select BOARD_LATE_INIT if CHAIN_OF_TRUST
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select SUPPORT_SPL
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select SUPPORT_TPL
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select PHYS_64BIT
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imply PANIC_HANG
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config TARGET_P3041DS
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bool "Support P3041DS"
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select PHYS_64BIT
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@ -1565,7 +1556,6 @@ config SYS_FSL_LBC_CLK_DIV
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Defines divider of platform clock(clock input to
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eLBC controller).
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source "board/freescale/c29xpcie/Kconfig"
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source "board/freescale/corenet_ds/Kconfig"
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source "board/freescale/mpc8536ds/Kconfig"
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source "board/freescale/mpc8541cds/Kconfig"
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@ -1,14 +0,0 @@
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if TARGET_C29XPCIE
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config SYS_BOARD
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default "c29xpcie"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "C29XPCIE"
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source "board/freescale/common/Kconfig"
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endif
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@ -1,10 +0,0 @@
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C29XPCIE BOARD
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M: Po Liu <po.liu@nxp.com>
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S: Maintained
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F: board/freescale/c29xpcie/
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F: include/configs/C29XPCIE.h
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F: configs/C29XPCIE_defconfig
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F: configs/C29XPCIE_NAND_defconfig
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F: configs/C29XPCIE_SPIFLASH_defconfig
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F: configs/C29XPCIE_NOR_SECBOOT_defconfig
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F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
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@ -1,25 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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ifdef MINIMAL
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obj-y += spl_minimal.o
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else
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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obj-y += c29xpcie.o
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obj-y += cpld.o
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obj-y += ddr.o
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endif
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obj-y += law.o
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obj-y += tlb.o
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@ -1,99 +0,0 @@
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Overview
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=========
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C29XPCIE board is a series of Freescale PCIe add-in cards to perform
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as public key crypto accelerator or secure key management module.
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It includes C293PCIE board, C293PCIE board and C291PCIE board.
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The Freescale C29x family is a high performance crypto co-processor.
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It combines a single e500v2 core with necessary SEC engines.
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(maximum core frequency 1000/1200 MHz).
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The C29xPCIE board features are as follows:
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Memory subsystem:
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- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
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- 64 Mbyte NOR flash single-chip memory
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- 4 Gbyte NAND flash memory
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- 1 Mbit AT24C1024 I2C EEPROM
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- 16 Mbyte SPI memory
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Interfaces:
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- 10/100/1000 BaseT Ethernet ports:
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- eTSEC1, RGMII: one 10/100/1000 port
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- eTSEC2, RGMII: one 10/100/1000 port
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- DUART interface:
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- DUART interface: supports two UARTs up to 115200 bps for
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console display
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Board connectors:
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- Mini-ITX power supply connector
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- JTAG/COP for debugging
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Physical Memory Map on C29xPCIE
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===============================
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Address Start Address End Memory type
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0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
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0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
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0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
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0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
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0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
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0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
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0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
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Serial Port Configuration on C29xPCIE
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=====================================
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Configure the serial port of the attached computer with the following values:
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-Data rate: 115200 bps
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-Number of data bits: 8
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-Parity: None
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-Number of Stop bits: 1
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-Flow Control: Hardware/None
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Settings of DIP-switch
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======================
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SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
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SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
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Note: 1 stands for 'off', 0 stands for 'on'
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Build and program U-Boot to NOR flash
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==================================
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1. Build u-boot.bin image example:
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export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
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make C293PCIE
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2. Program u-boot.bin into NOR flash
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=> tftp $loadaddr $uboot
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=> protect off eff40000 +$filesize
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=> erase eff40000 +$filesize
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=> cp.b $loadaddr eff40000 $filesize
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3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
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Alternate NOR bank
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==================
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There are four banks in C29XPCIE board, example to change bank booting:
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1. Program u-boot.bin into alternate NOR bank
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=> tftp $loadaddr $uboot
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=> protect off e9f40000 +$filesize
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=> erase e9f40000 +$filesize
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=> cp.b $loadaddr e9f40000 $filesize
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2. Switch to alternate NOR bank
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=> cpld_cmd reset altbank [bank]
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- [bank] bank value select 1-4
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- bank 1 on the flash 0x0000000~0x0ffffff
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- bank 2 on the flash 0x1000000~0x1ffffff
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- bank 3 on the flash 0x2000000~0x2ffffff
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- bank 4 on the flash 0x3000000~0x3ffffff
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or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
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Build and program U-Boot to SPI flash
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==================================
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1. Build u-boot-spi.bin image
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make C29xPCIE_SPIFLASH_config; make
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Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
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2. Program u-boot-spi.bin into SPI flash
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=> tftp $loadaddr $uboot-spi
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=> sf erase 0 100000
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=> sf write $loadaddr 0 $filesize
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3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
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@ -1,159 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <image.h>
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#include <init.h>
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#include <net.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <env.h>
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#include <miiphy.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <pci.h>
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#include <fsl_ifc.h>
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#include <asm/fsl_pci.h>
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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printf("Board: %sPCIe, ", cpu->name);
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printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
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return 0;
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}
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int board_early_init_f(void)
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{
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struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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/* Clock configuration to access CPLD using IFC(GPCM) */
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setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 1; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_64M, 1);
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif /* ifdef CONFIG_PCI */
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[2];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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/* Register 1G MDIO bus */
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void fdt_del_sec(void *blob, int offset)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
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CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
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+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
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fdt_del_node(blob, nodeoff);
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offset++;
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}
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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struct cpu_type *cpu;
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cpu = gd->arch.cpu;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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#if defined(CONFIG_PCI)
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FT_FSL_PCI_SETUP;
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#endif
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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if (cpu->soc_ver == SVR_C291)
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fdt_del_sec(blob, 1);
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else if (cpu->soc_ver == SVR_C292)
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fdt_del_sec(blob, 2);
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return 0;
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}
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#endif
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@ -1,133 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/**
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* Copyright 2013 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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* Po Liu <Po.Liu@freescale.com>
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*
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* This file provides support for the board-specific CPLD used on some Freescale
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* reference boards.
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*
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* The following macros need to be defined:
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*
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* CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
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* CPLD register map
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "cpld.h"
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/**
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* Set the boot bank to the alternate bank
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*/
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void cpld_set_altbank(u8 banksel)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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u8 reg11;
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reg11 = in_8(&cpld_data->flhcsr);
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switch (banksel) {
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case 1:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
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break;
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case 2:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
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break;
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case 3:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
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break;
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case 4:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
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break;
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default:
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printf("Invalid value! [1-4]\n");
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return;
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}
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udelay(100);
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do_reset(NULL, 0, 0, NULL);
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}
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/**
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* Set the boot bank to the default bank
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*/
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void cpld_set_defbank(void)
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{
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cpld_set_altbank(4);
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}
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
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printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
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printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
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printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
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printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
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printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
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printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
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printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
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printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
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printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
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printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
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printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
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printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
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printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
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printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
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printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
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putc('\n');
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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int rc = 0;
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unsigned char value;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (!strcmp(argv[2], "altbank") && argv[3]) {
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value = (u8)simple_strtoul(argv[3], NULL, 16);
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cpld_set_altbank(value);
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} else if (!argv[2])
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cpld_set_defbank();
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else
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cmd_usage(cmdtp);
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else
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rc = cmd_usage(cmdtp);
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return rc;
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}
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U_BOOT_CMD(
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cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
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||||
"Reset the board using the CPLD sequencer",
|
||||
"reset - hard reset to default bank 4\n"
|
||||
"cpld_cmd reset altbank [bank]- reset to alternate bank\n"
|
||||
" - [bank] bank value select 1-4\n"
|
||||
" - bank 1 on the flash 0x0000000~0x0ffffff\n"
|
||||
" - bank 2 on the flash 0x1000000~0x1ffffff\n"
|
||||
" - bank 3 on the flash 0x2000000~0x2ffffff\n"
|
||||
" - bank 4 on the flash 0x3000000~0x3ffffff\n"
|
||||
#ifdef DEBUG
|
||||
"cpld_cmd dump - display the CPLD registers\n"
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/**
|
||||
* Copyright 2013 Freescale Semiconductor
|
||||
* Author: Mingkai Hu <Mingkai.Hu@freescale.com>
|
||||
* Po Liu <Po.Liu@freescale.com>
|
||||
*
|
||||
* This file provides support for the ngPIXIS, a board-specific FPGA used on
|
||||
* some Freescale reference boards.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
|
||||
*/
|
||||
struct cpld_data {
|
||||
u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
|
||||
u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
|
||||
u8 hwver; /* 0x2 - Hardware Version Register */
|
||||
u8 cpldver; /* 0x3 - Software Version Register */
|
||||
u8 res[12];
|
||||
u8 rstcon; /* 0x10 - Reset control register */
|
||||
u8 flhcsr; /* 0x11 - Flash control and status Register */
|
||||
u8 wdcsr; /* 0x12 - Watchdog control and status Register */
|
||||
u8 wdkick; /* 0x13 - Watchdog kick Register */
|
||||
u8 fancsr; /* 0x14 - Fan control and status Register */
|
||||
u8 ledcsr; /* 0x15 - LED control and status Register */
|
||||
u8 misccsr; /* 0x16 - Misc control and status Register */
|
||||
u8 bootor; /* 0x17 - Boot configure override Register */
|
||||
u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
|
||||
u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
|
||||
u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
|
||||
u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
|
||||
};
|
||||
|
||||
#define CPLD_BANKSEL_EN 0x02
|
||||
#define CPLD_BANKSEL_MASK 0x3f
|
||||
#define CPLD_SELECT_BANK1 0xc0
|
||||
#define CPLD_SELECT_BANK2 0x80
|
||||
#define CPLD_SELECT_BANK3 0x40
|
||||
#define CPLD_SELECT_BANK4 0x00
|
||||
@ -1,106 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr_dimm_params.h>
|
||||
|
||||
#include "cpld.h"
|
||||
|
||||
#define C29XPCIE_HARDWARE_REVA 0x40
|
||||
/*
|
||||
* Micron MT41J128M16HA-15E
|
||||
* */
|
||||
dimm_params_t ddr_raw_timing = {
|
||||
.n_ranks = 1,
|
||||
.rank_density = 536870912u,
|
||||
.capacity = 536870912u,
|
||||
.primary_sdram_width = 32,
|
||||
.ec_sdram_width = 8,
|
||||
.registered_dimm = 0,
|
||||
.mirrored_dimm = 0,
|
||||
.n_row_addr = 14,
|
||||
.n_col_addr = 10,
|
||||
.n_banks_per_sdram_device = 8,
|
||||
.edc_config = 2,
|
||||
.burst_lengths_bitmask = 0x0c,
|
||||
|
||||
.tckmin_x_ps = 1650,
|
||||
.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
|
||||
.taa_ps = 14050,
|
||||
.twr_ps = 15000,
|
||||
.trcd_ps = 13500,
|
||||
.trrd_ps = 75000,
|
||||
.trp_ps = 13500,
|
||||
.tras_ps = 40000,
|
||||
.trc_ps = 49500,
|
||||
.trfc_ps = 160000,
|
||||
.twtr_ps = 75000,
|
||||
.trtp_ps = 75000,
|
||||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 30000,
|
||||
};
|
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
|
||||
unsigned int controller_number,
|
||||
unsigned int dimm_number)
|
||||
{
|
||||
const char dimm_model[] = "Fixed DDR on board";
|
||||
|
||||
if ((controller_number == 0) && (dimm_number == 0)) {
|
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
|
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
|
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
|
||||
int i;
|
||||
|
||||
popts->clk_adjust = 4;
|
||||
popts->cpo_override = 0x1f;
|
||||
popts->write_data_delay = 4;
|
||||
popts->half_strength_driver_enable = 1;
|
||||
popts->bstopre = 0x3cf;
|
||||
popts->quad_rank_present = 1;
|
||||
popts->rtt_override = 1;
|
||||
popts->rtt_override_value = 1;
|
||||
popts->dynamic_power = 1;
|
||||
/* Write leveling override */
|
||||
popts->wrlvl_en = 1;
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
popts->wrlvl_start = 0x4;
|
||||
popts->trwt_override = 1;
|
||||
popts->trwt = 0;
|
||||
|
||||
if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
|
||||
popts->ecc_mode = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
||||
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
|
||||
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
|
||||
}
|
||||
}
|
||||
|
||||
void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
|
||||
{
|
||||
int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
|
||||
sizeof(generic_spd_eeprom_t));
|
||||
|
||||
if (ret) {
|
||||
printf("DDR: failed to read SPD from address %u\n",
|
||||
i2c_address);
|
||||
memset(spd, 0, sizeof(generic_spd_eeprom_t));
|
||||
}
|
||||
}
|
||||
@ -1,18 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
|
||||
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
|
||||
SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
|
||||
LAW_TRGT_IF_PLATFORM_SRAM),
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
@ -1,81 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clock_legacy.h>
|
||||
#include <console.h>
|
||||
#include <env_internal.h>
|
||||
#include <init.h>
|
||||
#include <ns16550.h>
|
||||
#include <malloc.h>
|
||||
#include <mmc.h>
|
||||
#include <nand.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
return CONFIG_SYS_L2_SIZE;
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
console_init_f();
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
/* Pointer is writable since we allocated a register for it */
|
||||
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
|
||||
bd_t *bd;
|
||||
|
||||
memset(gd, 0, sizeof(gd_t));
|
||||
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
|
||||
memset(bd, 0, sizeof(bd_t));
|
||||
gd->bd = bd;
|
||||
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
|
||||
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
|
||||
|
||||
arch_cpu_init();
|
||||
get_clocks();
|
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
|
||||
CONFIG_SPL_RELOC_MALLOC_SIZE);
|
||||
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
|
||||
|
||||
/* relocate environment function pointers etc. */
|
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||
(uchar *)SPL_ENV_ADDR);
|
||||
gd->env_addr = (ulong)(SPL_ENV_ADDR);
|
||||
gd->env_valid = ENV_VALID;
|
||||
|
||||
i2c_init_all();
|
||||
|
||||
dram_init();
|
||||
|
||||
#ifdef CONFIG_SPL_NAND_BOOT
|
||||
puts("TPL\n");
|
||||
#else
|
||||
puts("SPL\n");
|
||||
#endif
|
||||
|
||||
nand_boot();
|
||||
}
|
||||
@ -1,63 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <mpc85xx.h>
|
||||
#include <asm/io.h>
|
||||
#include <ns16550.h>
|
||||
#include <nand.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
|
||||
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
|
||||
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
|
||||
#endif
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot...\n");
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
puts("SPL\n");
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
@ -1,84 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
#endif
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_64K, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64K, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
|
||||
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
|
||||
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 7, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || \
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
||||
0, 8, BOOKE_PAGESZ_256M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
||||
0, 9, BOOKE_PAGESZ_256M, 1),
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
|
||||
0, 12, BOOKE_PAGESZ_256K, 1)
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -1,70 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x11001000
|
||||
CONFIG_ENV_SIZE=0x100000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_TEXT_BASE=0xFF800000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_C29XPCIE=y
|
||||
CONFIG_SYS_CUSTOM_LDSCRIPT=y
|
||||
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
# CONFIG_SPL_FRAMEWORK is not set
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_TPL_ENV_SUPPORT=y
|
||||
CONFIG_TPL_I2C_SUPPORT=y
|
||||
CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
CONFIG_TPL_NAND_SUPPORT=y
|
||||
CONFIG_TPL_SERIAL_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,55 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_C29XPCIE=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_SOFTWARE_EXP=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,57 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_C29XPCIE=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_SOFTWARE_EXP=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,55 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_C29XPCIE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,53 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_C29XPCIE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,443 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* C29XPCIE board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#ifdef CONFIG_SPIFLASH
|
||||
#define CONFIG_RAMBOOT_SPIFLASH
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_NAND_INIT
|
||||
#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
|
||||
#define CONFIG_SPL_COMMON_INIT_DDR
|
||||
#define CONFIG_SPL_MAX_SIZE (128 << 10)
|
||||
#define CONFIG_TPL_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
|
||||
#elif defined(CONFIG_SPL_BUILD)
|
||||
#define CONFIG_SPL_INIT_MINIMAL
|
||||
#define CONFIG_SPL_NAND_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_MAX_SIZE 8192
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
|
||||
#endif
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
#define CONFIG_TPL_PAD_TO 0x20000
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
|
||||
#elif defined(CONFIG_SPL_BUILD)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
/*
|
||||
* PCI Windows
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
/* controller 1, Slot 1, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "Slot 1"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_DDR_CLK_FREQ 100000000
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_ADDR_MAP 1
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x50
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
|
||||
/* DDR ECC Setup*/
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 512
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
/* Platform SRAM setting */
|
||||
#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
|
||||
#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
|
||||
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
|
||||
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
/* NOR Flash on IFC */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xec000000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
|
||||
|
||||
/* 16Bit NOR Flash - S29GL512S10TFI01 */
|
||||
#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
|
||||
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
/* CFI for NOR Flash */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
|
||||
|
||||
/* 8Bit NAND Flash - K9F1G08U0B */
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_NAND \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
|
||||
| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
|
||||
| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
|
||||
| CSOR_NAND_PB(128)) /*128 Pages Per Block*/
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
|
||||
FTIM0_NAND_TWP(0x0c) | \
|
||||
FTIM0_NAND_TWCHT(0x08) | \
|
||||
FTIM0_NAND_TWH(0x06))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
|
||||
FTIM1_NAND_TWBE(0x1d) | \
|
||||
FTIM1_NAND_TRR(0x08) | \
|
||||
FTIM1_NAND_TRP(0x0c))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
|
||||
/* Set up IFC registers for boot location NOR/NAND */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
|
||||
/* CPLD on IFC, selected by CS2 */
|
||||
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
|
||||
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
|
||||
| CONFIG_SYS_CPLD_BASE)
|
||||
|
||||
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_CSOR2 0x0
|
||||
/* CPLD Timing parameters for IFC CS2 */
|
||||
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x8) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Config the L2 Cache as L2 SRAM
|
||||
*/
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#define CONFIG_SYS_L2_SIZE (256 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
|
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
|
||||
#elif defined(CONFIG_MTD_RAW_NAND)
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#define CONFIG_SYS_L2_SIZE (256 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
|
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#define CONFIG_SYS_L2_SIZE (256 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
|
||||
#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C EEPROM */
|
||||
/* enable read and write access to EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* eSPI - Enhanced SPI */
|
||||
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
|
||||
/* Default mode is RGMII mode */
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 2
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#elif defined(CONFIG_MTD_RAW_NAND)
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
|
||||
#else
|
||||
#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=1e00000\0" \
|
||||
"fdtfile=name/of/device-tree.dtb\0" \
|
||||
"othbootargs=ramdisk_size=600000\0" \
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user