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riscv: Fix clear bss loop in the start-up code

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For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
This commit is contained in:
Rick Chen 2019-11-14 13:52:27 +08:00 committed by Andes
parent 31dae22faa
commit 444c46413f
3 changed files with 4 additions and 4 deletions
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4
arch/riscv/cpu/start.S
View File

@ -174,7 +174,7 @@ spl_clear_bss:
spl_clear_bss_loop: spl_clear_bss_loop:
SREG zero, 0(t0) SREG zero, 0(t0)
addi t0, t0, REGBYTES addi t0, t0, REGBYTES
bne t0, t1, spl_clear_bss_loop blt t0, t1, spl_clear_bss_loop
spl_stack_gd_setup: spl_stack_gd_setup:
jal spl_relocate_stack_gd jal spl_relocate_stack_gd
@ -324,7 +324,7 @@ clear_bss:
clbss_l: clbss_l:
SREG zero, 0(t0) /* clear loop... */ SREG zero, 0(t0) /* clear loop... */
addi t0, t0, REGBYTES addi t0, t0, REGBYTES
bne t0, t1, clbss_l blt t0, t1, clbss_l
relocate_secondary_harts: relocate_secondary_harts:
#ifdef CONFIG_SMP #ifdef CONFIG_SMP

2
arch/riscv/cpu/u-boot-spl.lds
View File

@ -76,7 +76,7 @@ SECTIONS
.bss : { .bss : {
__bss_start = .; __bss_start = .;
*(.bss*) *(.bss*)
. = ALIGN(4); . = ALIGN(8);
__bss_end = .; __bss_end = .;
} > .bss_mem } > .bss_mem
} }

2
arch/riscv/cpu/u-boot.lds
View File

@ -82,7 +82,7 @@ SECTIONS
.bss : { .bss : {
__bss_start = .; __bss_start = .;
*(.bss*) *(.bss*)
. = ALIGN(4); . = ALIGN(8);
__bss_end = .; __bss_end = .;
} }
} }