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arm: socfpga: clock: Clean up bit definitions

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Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Marek Vasut
2014-09-16 17:21:00 +02:00
parent 5d8ad0cd3a
commit 44428ab6ab
3 changed files with 294 additions and 274 deletions
Download Patch File Download Diff File Expand all files Collapse all files

118
arch/arm/cpu/armv7/socfpga/clock_manager.c
View File

@@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#define CLKMGR_BYPASS_ENABLE 1
#define CLKMGR_BYPASS_DISABLE 0
#define CLKMGR_STAT_IDLE 0
#define CLKMGR_STAT_BUSY 1
#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
#define CLEAR_BGP_EN_PWRDN \
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
#define VCO_EN_BASE \
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
@@ -130,14 +111,8 @@ void cm_basic_init(const cm_config_t *cfg)
writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */
cm_write_bypass(
CLKMGR_BYPASS_PERPLLSRC_SET(
CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_SDRPLLSRC_SET(
CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
CLKMGR_BYPASS_MAINPLL);
/*
* Put all plls VCO registers back to reset value.
@@ -172,19 +147,14 @@ void cm_basic_init(const cm_config_t *cfg)
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->main_pll.vco);
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->main_pll.vco);
writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->per_pll.vco);
writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll.vco);
writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll.vco);
/*
* Time starts here
@@ -234,18 +204,16 @@ void cm_basic_init(const cm_config_t *cfg)
/* Enable vco */
/* main pll vco */
writel(cfg->main_vco_base | VCO_EN_BASE,
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->main_pll.vco);
/* periferal pll */
writel(cfg->peri_vco_base | VCO_EN_BASE,
writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->per_pll.vco);
/* sdram pll vco */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll.vco);
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */
writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@@ -296,8 +264,8 @@ void cm_basic_init(const cm_config_t *cfg)
&clock_manager_base->per_pll.vco);
/* assert sdram outresetall */
writel(cfg->sdram_vco_base | VCO_EN_BASE|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
&clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */
@@ -309,9 +277,8 @@ void cm_basic_init(const cm_config_t *cfg)
&clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll.vco);
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->sdr_pll.vco);
/*
* now that we've toggled outreset all, all the clocks
@@ -335,18 +302,10 @@ void cm_basic_init(const cm_config_t *cfg)
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */
cm_write_bypass(
CLKMGR_BYPASS_PERPLLSRC_SET(
CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_SDRPLLSRC_SET(
CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
cm_write_bypass(0);
/* clear safe mode */
cm_write_ctrl(readl(&clock_manager_base->ctrl) |
CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
/*
* now that safe mode is clear with clocks gated
@@ -367,9 +326,11 @@ static unsigned int cm_get_main_vco_clk_hz(void)
/* get the main VCO clock */
reg = readl(&clock_manager_base->main_pll.vco);
clock = CONFIG_HPS_CLK_OSC1_HZ /
(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
clock = CONFIG_HPS_CLK_OSC1_HZ;
clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock;
}
@@ -380,7 +341,8 @@ static unsigned int cm_get_per_vco_clk_hz(void)
/* identify PER PLL clock source */
reg = readl(&clock_manager_base->per_pll.vco);
reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
@@ -390,8 +352,10 @@ static unsigned int cm_get_per_vco_clk_hz(void)
/* get the PER VCO clock */
reg = readl(&clock_manager_base->per_pll.vco);
clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock;
}
@@ -416,7 +380,8 @@ unsigned long cm_get_sdram_clk_hz(void)
/* identify SDRAM PLL clock source */
reg = readl(&clock_manager_base->sdr_pll.vco);
reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
@@ -426,12 +391,15 @@ unsigned long cm_get_sdram_clk_hz(void)
/* get the SDRAM VCO clock */
reg = readl(&clock_manager_base->sdr_pll.vco);
clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
/* get the SDRAM (DDR_DQS) clock */
reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
clock /= (reg + 1);
return clock;
@@ -443,7 +411,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
/* identify the source of L4 SP clock */
reg = readl(&clock_manager_base->main_pll.l4src);
reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
clock = cm_get_main_vco_clk_hz();
@@ -463,7 +432,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
/* get the L4 SP clock which supplied to UART */
reg = readl(&clock_manager_base->main_pll.maindiv);
reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
clock = clock / (1 << reg);
return clock;
@@ -475,7 +445,8 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
/* identify the source of MMC clock */
reg = readl(&clock_manager_base->per_pll.src);
reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
@@ -504,7 +475,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
/* identify the source of QSPI clock */
reg = readl(&clock_manager_base->per_pll.src);
reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;

174
arch/arm/cpu/armv7/socfpga/spl.c
View File

@@ -19,6 +19,31 @@
DECLARE_GLOBAL_DATA_PTR;
#define MAIN_VCO_BASE ( \
(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
)
#define PERI_VCO_BASE ( \
(CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
(CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
)
#define SDR_VCO_BASE ( \
(CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
(CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
)
u32 spl_boot_device(void)
{
return BOOT_DEVICE_RAM;
@@ -33,86 +58,87 @@ void spl_board_init(void)
cm_config_t cm_default_cfg = {
/* main group */
MAIN_VCO_BASE,
CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */
PERI_VCO_BASE,
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
CLKMGR_PERPLLGRP_SRC_QSPI_SET(
CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
CLKMGR_PERPLLGRP_SRC_NAND_SET(
CONFIG_HPS_PERPLLGRP_SRC_NAND) |
CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */
SDR_VCO_BASE,
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
};
debug("Freezing all I/O banks\n");