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powerpc/85xx: Add workaround for erratum CPU-A003999

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Erratum A-003999: Running Floating Point instructions requires special
initialization.

Impact:
Floating point arithmetic operations may result in an incorrect value.

Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-11-22 06:51:15 -06:00
parent a63d965275
commit 43f082bb7f
4 changed files with 21 additions and 0 deletions
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3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -53,6 +53,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n"); puts("Work-around for Erratum CPU22 enabled\n");
#endif #endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif #endif

6
arch/powerpc/cpu/mpc85xx/release.S
View File

@ -68,6 +68,12 @@ __secondary_start_page:
mtspr SPRN_HID1,r3 mtspr SPRN_HID1,r3
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
mfspr r3,977
oris r3,r3,0x0100
mtspr 977,r3
#endif
/* Enable branch prediction */ /* Enable branch prediction */
lis r3,BUCSR_ENABLE@h lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l ori r3,r3,BUCSR_ENABLE@l

6
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -253,6 +253,12 @@ l2_disabled:
mtspr HID1,r0 mtspr HID1,r0
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
mfspr r3,977
oris r3,r3,0x0100
mtspr 977,r3
#endif
/* Enable Branch Prediction */ /* Enable Branch Prediction */
#if defined(CONFIG_BTB) #if defined(CONFIG_BTB)
lis r0,BUCSR_ENABLE@h lis r0,BUCSR_ENABLE@h

6
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -313,6 +313,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P2041) #elif defined(CONFIG_PPC_P2041)
#define CONFIG_MAX_CPUS 4 #define CONFIG_MAX_CPUS 4
@ -331,6 +332,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P3041) #elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4 #define CONFIG_MAX_CPUS 4
@ -349,6 +351,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P3060) #elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8 #define CONFIG_MAX_CPUS 8
@ -364,6 +367,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P4040) #elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4 #define CONFIG_MAX_CPUS 4
@ -374,6 +378,7 @@
#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P4080) #elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8 #define CONFIG_MAX_CPUS 8
@ -402,6 +407,7 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES9 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
/* P5010 is single core version of P5020 */ /* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010) #elif defined(CONFIG_PPC_P5010)