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* Patch by Robert Schwebel, 21 Jan 2003:

Browse Source 
- Add support for Innokom board
  - Don't complain if "install" fails
  - README cleanup (remove duplicated lines)
  - Update PXA header files

* Add documentation for existing POST code (doc/README.POST)

* Patch by Laudney Ren, 15 Jan 2003:
  Fix handling of redundand environment in "tools/envcrc.c"

* Patch by Detlev Zundel, 28 Feb 2003:
  Add bedbug support for 824x systems

* Add support for 16 MB flash configuration of TRAB board

* Patch by Erwin Rol, 27 Feb 2003:
  Add support for RTEMS

* Add image information to README

* Fix dual PCMCIA slot support (when running with just one
  slot populated)

* Add VFD type detection to trab board

* extend drivers/cs8900.c driver to synchronize  ethaddr  environment
  variable with value in the EEPROM
This commit is contained in:
wdenk
2003-03-06 00:02:04 +00:00
parent 6069ff2653
commit 43d9616cff
26 changed files with 3495 additions and 391 deletions
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47
board/innokom/Makefile Normal file
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#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := innokom.o flash.o
SOBJS := memsetup.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

16
board/innokom/config.mk Normal file
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#
# Linux-Kernel is expected to be at c000'8000, entry c000'8000
#
# we load ourself to c170'0000, the upper 1 MB of second bank
#
# download areas is c800'0000
#
# This is the address where U-Boot lives in flash:
#TEXT_BASE = 0
# FIXME: armboot does only work correctly when being compiled
# for the addresses _after_ relocation to RAM!! Otherwhise the
# .bss segment is assumed in flash...
TEXT_BASE = 0xa1fe0000

377
board/innokom/flash.c Normal file
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/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/pxa-regs.h>
#define FLASH_BANK_SIZE 0x02000000
#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/**
* flash_init: - initialize data structures for flash chips
*
* @return: size of the flash
*/
ulong flash_init(void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(INTEL_MANUFACT & FLASH_VENDMASK) |
(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
switch (i) {
case 0:
flashbase = PHYS_FLASH_1;
break;
default:
panic("configured to many flash banks!\n");
break;
}
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors */
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
&flash_info[0]);
#ifdef CFG_ENV_IS_IN_FLASH
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#endif
return size;
}
/**
* flash_print_info: - print information about the flash situation
*
* @param info:
*/
void flash_print_info (flash_info_t *info)
{
int i, j;
for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
switch (info->flash_id & FLASH_VENDMASK) {
case (INTEL_MANUFACT & FLASH_VENDMASK):
printf("Intel: ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
printf("28F128J3 (128Mbit)\n");
break;
default:
printf("Unknown Chip Type\n");
return;
}
printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) printf ("\n ");
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
info++;
}
}
/**
* flash_erase: - erase flash sectors
*
*/
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
int rc = ERR_OK;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) prot++;
}
if (prot) return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
if (info->protect[sect] == 0) { /* not protected */
u32 * volatile addr = (u32 * volatile)(info->start[sect]);
/* erase sector: */
/* The strata flashs are aligned side by side on */
/* the data bus, so we have to write the commands */
/* to both chips here: */
*addr = 0x00200020; /* erase setup */
*addr = 0x00D000D0; /* erase confirm */
while ((*addr & 0x00800080) != 0x00800080) {
if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase*/
*addr = 0x00FF00FF; /* read mode */
rc = ERR_TIMOUT;
goto outahere;
}
}
*addr = 0x00500050; /* clear status register cmd. */
*addr = 0x00FF00FF; /* resest to read mode */
}
printf("ok.\n");
}
if (ctrlc()) printf("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay_masked(10000);
if (flag) enable_interrupts();
return rc;
}
/**
* write_word: - copy memory to flash
*
* @param info:
* @param dest:
* @param data:
* @return:
*/
static int write_word (flash_info_t *info, ulong dest, ushort data)
{
ushort *addr = (ushort *)dest, val;
int rc = ERR_OK;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts();
/* clear status register command */
*addr = 0x50;
/* program set-up command */
*addr = 0x40;
/* latch address/data */
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
/* wait while polling the status register */
while(((val = *addr) & 0x80) != 0x80) {
if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
*addr = 0xB0; /* suspend program command */
goto outahere;
}
}
if(val & 0x1A) { /* check for error */
printf("\nFlash write error %02x at address %08lx\n",
(int)val, (unsigned long)dest);
if(val & (1<<3)) {
printf("Voltage range error.\n");
rc = ERR_PROG_ERROR;
goto outahere;
}
if(val & (1<<1)) {
printf("Device protect error.\n");
rc = ERR_PROTECTED;
goto outahere;
}
if(val & (1<<4)) {
printf("Programming error.\n");
rc = ERR_PROG_ERROR;
goto outahere;
}
rc = ERR_PROG_ERROR;
goto outahere;
}
outahere:
*addr = 0xFF; /* read array command */
if (flag) enable_interrupts();
return rc;
}
/**
* write_buf: - Copy memory to flash.
*
* @param info:
* @param src: source of copy transaction
* @param addr: where to copy to
* @param cnt: number of bytes to copy
*
* @return error code
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp;
ushort data;
int l;
int i, rc;
wp = (addr & ~1); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data >> 8) | (*(uchar *)cp << 8);
}
for (; i<2 && cnt>0; ++i) {
data = (data >> 8) | (*src++ << 8);
--cnt;
++cp;
}
for (; cnt==0 && i<2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *)cp << 8);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 2;
}
/*
* handle word aligned part
*/
while (cnt >= 2) {
/* data = *((vushort*)src); */
data = *((ushort*)src);
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 0) return ERR_OK;
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
data = (data >> 8) | (*src++ << 8);
--cnt;
}
for (; i<2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *)cp << 8);
}
return write_word(info, wp, data);
}

139
board/innokom/innokom.c Normal file
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/*
* (C) Copyright 2002
* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
* Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
* Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/pxa-regs.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
/*
* Miscelaneous platform dependent initialisations
*/
/**
* board_init: - setup some data structures
*
* @return: 0 in case of success
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of Innokom board */
gd->bd->bi_arch_number = 258;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
/**
* dram_init: - setup dynamic RAM
*
* @return: 0 in case of success
*/
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
/**
* innokom_set_led: - switch LEDs on or off
*
* @param led: LED to switch (0,1,2)
* @param state: switch on (1) or off (0)
*/
void innokom_set_led(int led, int state)
{
switch(led) {
/*
case 0: if (state==1) {
GPCR0 |= CSB226_USER_LED0;
} else if (state==0) {
GPSR0 |= CSB226_USER_LED0;
}
break;
case 1: if (state==1) {
GPCR0 |= CSB226_USER_LED1;
} else if (state==0) {
GPSR0 |= CSB226_USER_LED1;
}
break;
case 2: if (state==1) {
GPCR0 |= CSB226_USER_LED2;
} else if (state==0) {
GPSR0 |= CSB226_USER_LED2;
}
break;
*/
}
return;
}
/**
* show_boot_progress: - indicate state of the boot process
*
* @param status: Status number - see README for details.
*
* The CSB226 does only have 3 LEDs, so we switch them on at the most
* important states (1, 5, 15).
*/
void show_boot_progress (int status)
{
switch(status) {
/*
case 1: csb226_set_led(0,1); break;
case 5: csb226_set_led(1,1); break;
case 15: csb226_set_led(2,1); break;
*/
}
return;
}

429
board/innokom/memsetup.S Normal file
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/*
* Most of this taken from Redboot hal_platform_setup.h with cleanup
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
* board/cradle/memsetup.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
DRAM_SIZE: .long CFG_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
/*
* Memory setup
*/
.globl memsetup
memsetup:
mov r10, lr
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
ldr r1, =CFG_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CFG_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CFG_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CFG_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =CFG_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =CFG_GPCR2_VAL
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =CFG_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =CFG_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =CFG_GPDR2_VAL
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =CFG_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =CFG_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =CFG_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =CFG_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =CFG_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =CFG_GAFR2_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
ldr r1, =CFG_PSSR_VAL
str r1, [r0]
/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
/* */
/* ldr r1, =LED_BLANK */
/* mov r0, #0xFF */
/* str r0, [r1] / turn on hex leds */
/* */
/*loop: */
/* */
/* ldr r0, =0xB0070001 */
/* ldr r1, =_LED */
/* str r0, [r1] / hex display */
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
/* Chapter 10. */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
mem_init:
ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
/* ---------------------------------------------------------------- */
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
ldr r2, =CFG_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
ldr r2, =CFG_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
ldr r2, =CFG_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
ldr r2, =CFG_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
ldr r2, =CFG_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
ldr r2, =CFG_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
ldr r2, =CFG_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
ldr r2, =CFG_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
ldr r2, =CFG_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
ldr r2, =CFG_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
/* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DIR field. */
ldr r4, =0x03ca4fff
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
ldr r4, =0x03ca4030
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Note: preserve the mdrefr value in r4 */
/* ---------------------------------------------------------------- */
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
/* ---------------------------------------------------------------- */
/* Initialize SXCNFG register. Assert the enable bits */
/* Write SXMRS to cause an MRS command to all enabled banks of */
/* synchronous static memory. Note that SXLCR need not be written */
/* at this time. */
/* FIXME: we use async mode for now */
/* ---------------------------------------------------------------- */
/* Step 4: Initialize SDRAM */
/* ---------------------------------------------------------------- */
/* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4b: de-assert MDREFR:SLFRSH. */
bic r4, r4, #(MDREFR_SLFRSH)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4c: assert MDREFR:E1PIN and E0PIO */
orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
/* 100..200 <20>sec. */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */
/* SDRAM, as commonly specified in the power up sequence */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
ldr r3, [r1, #MDCNFG_OFFSET]
orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
str r3, [r1, #MDCNFG_OFFSET]
/* Step 4h: Write MDMRS. */
ldr r2, =CFG_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
initirqs:
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
ldr r2, =ICLR
str r1, [r2]
ldr r2, =ICMR /* mask all interrupts at the controller */
str r1, [r2]
/* ---------------------------------------------------------------- */
/* Clock initialisation */
/* ---------------------------------------------------------------- */
initclks:
/* Disable the peripheral clocks, and set the core clock frequency */
/* (hard-coding at 398.12MHz for now). */
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
ldr r1, =CKEN
mov r2, #0
str r2, [r1]
/* default value in case no valid rotary switch setting is found */
ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
/* ... and write the core clock config register */
ldr r1, =CCCR
str r2, [r1]
/* enable the 32Khz oscillator for RTC and PowerManager */
/*
ldr r1, =OSCC
mov r2, #OSCC_OON
str r2, [r1]
*/
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
ldr r2, [r1]
ands r2, r2, #1
beq 60b
/* ---------------------------------------------------------------- */
/* */
/* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
str r8, [r1]
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
mov r1, #0
str r1, [r0]
/* FIXME */
#define NODEBUG
#ifdef NODEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
/* End memsetup */
/* ---------------------------------------------------------------- */
endmemsetup:
mov pc, lr

53
board/innokom/u-boot.lds Normal file
View File

@@ -0,0 +1,53 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/xscale/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
armboot_end_data = .;
. = ALIGN(4);
.bss : { *(.bss) }
armboot_end = .;
}

260
board/r360mpi/flash.c
View File

@@ -24,10 +24,12 @@
* MA 02111-1307 USA
*/
/* #define DEBUG */
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
@@ -52,44 +54,44 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info);
static int write_data (flash_info_t *info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t *info);
static ulong flash_get_size (FPW * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
size_b0, size_b0 << 20);
}
/* Remap FLASH according to real size */
@@ -97,24 +99,24 @@ unsigned long flash_init (void)
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
(void) flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + CFG_MONITOR_LEN - 1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SIZE-1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
@@ -124,7 +126,7 @@ unsigned long flash_init (void)
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
@@ -141,7 +143,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
void flash_print_info (flash_info_t * info)
{
int i;
@@ -151,31 +153,39 @@ void flash_print_info (flash_info_t *info)
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
printf ("28F320J3A\n"); break;
case FLASH_28F640J3A:
printf ("28F640J3A\n"); break;
case FLASH_28F128J3A:
printf ("28F128J3A\n"); break;
default: printf ("Unknown Chip Type\n"); break;
case FLASH_28F320J3A:
printf ("28F320J3A\n");
break;
case FLASH_28F640J3A:
printf ("28F640J3A\n");
break;
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
@@ -192,49 +202,53 @@ void flash_print_info (flash_info_t *info)
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info)
static ulong flash_get_size (FPW * addr, flash_info_t * info)
{
FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW)0x00AA00AA;
addr[0x2AAA] = (FPW)0x00550055;
addr[0x5555] = (FPW)0x00900090;
addr[0x5555] = (FPW) 0x00AA00AA;
addr[0x2AAA] = (FPW) 0x00550055;
addr[0x5555] = (FPW) 0x00900090;
value = addr[0];
switch (value) {
case (FPW)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
switch (value) {
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW)0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
value = addr[1]; /* device ID */
value = addr[1]; /* device ID */
switch (value) {
case (FPW)INTEL_ID_28F320J3A:
info->flash_id += FLASH_28F320J3A;
info->sector_count = 32;
info->size = 0x00400000;
break; /* => 4 MB */
debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
case (FPW)INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x00800000;
break; /* => 8 MB */
switch (value) {
case (FPW) INTEL_ID_28F320J3A:
info->flash_id += FLASH_28F320J3A;
info->sector_count = 32;
info->size = 0x00400000;
break; /* => 4 MB */
case (FPW)INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x01000000;
break; /* => 16 MB */
case (FPW) INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x00800000;
break; /* => 8 MB */
case (FPW) INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x01000000;
break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
@@ -243,11 +257,11 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
if (info->sector_count > CFG_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
}
addr[0] = (FPW)0x00FF00FF; /* restore read mode */
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (info->size);
}
@@ -256,7 +270,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, now, last;
@@ -279,7 +293,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
@@ -293,44 +307,44 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
start = get_timer (0);
last = start;
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *)(info->start[sect]);
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
*addr = (FPW)0x00500050; /* clear status register */
*addr = (FPW)0x00200020; /* erase setup */
*addr = (FPW)0x00D000D0; /* erase confirm */
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW)0x00B000B0; /* suspend erase */
*addr = (FPW)0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
*addr = (FPW)0x00FF00FF; /* reset to read mode */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
}
}
printf (" done\n");
@@ -345,15 +359,12 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
* 4 - Flash not identified
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
#if 0
int count, i, l, rc, port_width;
#else
int i, l, rc, port_width;
#endif
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
@@ -372,19 +383,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i<port_width && cnt>0; ++i) {
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
if ((rc = write_data (info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
@@ -393,26 +404,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
/*
* handle word aligned part
*/
#if 0
count = 0;
#endif
while (cnt >= port_width) {
data = 0;
for (i=0; i<port_width; ++i) {
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data(info, wp, data)) != 0) {
if ((rc = write_data (info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
wp += port_width;
cnt -= port_width;
#if 0
if (count++ > 0x20000)
{
putc('.');
count = 0;
}
#endif
}
if (cnt == 0) {
@@ -423,15 +424,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data(info, wp, data));
return (write_data (info, wp, data));
}
/*-----------------------------------------------------------------------
@@ -440,39 +441,38 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, FPW data)
static int write_data (flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *)dest;
FPWV *addr = (FPWV *) dest;
ulong status;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
*addr = (FPW)0x00400040; /* write setup */
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
start = get_timer (0);
while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW)0x00FF00FF; /* restore read mode */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW)0x00FF00FF; /* restore read mode */
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}