Merge branch 'master' of git://www.denx.de/git/u-boot-imx
This commit is contained in:
Tom Rini
commit
43ade93bdb
@ -1032,8 +1032,6 @@ source "arch/arm/mach-keystone/Kconfig"
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source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-litesom/Kconfig"
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source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/cpu/armv7/ls102xa/Kconfig"
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source "arch/arm/cpu/armv7/ls102xa/Kconfig"
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@ -59,7 +59,6 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
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machine-$(CONFIG_ARCH_KEYSTONE) += keystone
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machine-$(CONFIG_ARCH_KEYSTONE) += keystone
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# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
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# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
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machine-$(CONFIG_KIRKWOOD) += kirkwood
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machine-$(CONFIG_KIRKWOOD) += kirkwood
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machine-$(CONFIG_LITESOM) += litesom
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machine-$(CONFIG_ARCH_MESON) += meson
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machine-$(CONFIG_ARCH_MESON) += meson
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
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# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
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@ -35,6 +35,13 @@ config MX6UL
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select ROM_UNIFIED_SECTIONS
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select ROM_UNIFIED_SECTIONS
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bool
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bool
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config MX6UL_LITESOM
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bool
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select MX6UL
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select DM
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select DM_THERMAL
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select SUPPORT_SPL
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config MX6ULL
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config MX6ULL
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bool
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bool
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select MX6UL
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select MX6UL
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@ -125,6 +132,10 @@ config TARGET_KOSAGI_NOVENA
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select BOARD_LATE_INIT
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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select SUPPORT_SPL
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config TARGET_MCCMON6
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bool "mccmon6"
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select SUPPORT_SPL
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config TARGET_MX6CUBOXI
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config TARGET_MX6CUBOXI
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bool "Solid-run mx6 boards"
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bool "Solid-run mx6 boards"
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select BOARD_LATE_INIT
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select BOARD_LATE_INIT
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@ -248,7 +259,7 @@ config TARGET_PICO_IMX6UL
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config TARGET_LITEBOARD
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config TARGET_LITEBOARD
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bool "Grinn liteBoard (i.MX6UL)"
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bool "Grinn liteBoard (i.MX6UL)"
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select BOARD_LATE_INIT
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select BOARD_LATE_INIT
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select LITESOM
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select MX6UL_LITESOM
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config TARGET_PLATINUM_PICON
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config TARGET_PLATINUM_PICON
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bool "platinum-picon"
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bool "platinum-picon"
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@ -361,6 +372,7 @@ source "board/phytec/pcm058/Kconfig"
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source "board/gateworks/gw_ventana/Kconfig"
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source "board/gateworks/gw_ventana/Kconfig"
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source "board/kosagi/novena/Kconfig"
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source "board/kosagi/novena/Kconfig"
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source "board/samtec/vining_2000/Kconfig"
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source "board/samtec/vining_2000/Kconfig"
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source "board/liebherr/mccmon6/Kconfig"
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source "board/seco/Kconfig"
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source "board/seco/Kconfig"
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source "board/solidrun/mx6cuboxi/Kconfig"
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source "board/solidrun/mx6cuboxi/Kconfig"
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source "board/technexion/pico-imx6ul/Kconfig"
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source "board/technexion/pico-imx6ul/Kconfig"
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@ -10,3 +10,4 @@
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obj-y := soc.o clock.o
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obj-y := soc.o clock.o
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obj-$(CONFIG_SPL_BUILD) += ddr.o
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obj-$(CONFIG_SPL_BUILD) += ddr.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
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@ -315,6 +315,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6dl-icore-rqs.dtb \
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imx6dl-icore-rqs.dtb \
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imx6q-icore.dtb \
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imx6q-icore.dtb \
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imx6q-icore-rqs.dtb \
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imx6q-icore-rqs.dtb \
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imx6sx-sabreauto.dtb \
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imx6ul-geam-kit.dtb
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imx6ul-geam-kit.dtb
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dtb-$(CONFIG_MX7) += imx7-colibri.dtb
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dtb-$(CONFIG_MX7) += imx7-colibri.dtb
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@ -114,16 +114,16 @@
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MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
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MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
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MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
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MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
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MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX53_PAD_FEC_MDC__FEC_MDC 0x4
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
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MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
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MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
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MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
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MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
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1558
arch/arm/dts/imx6sx-pinfunc.h
Normal file
1558
arch/arm/dts/imx6sx-pinfunc.h
Normal file
File diff suppressed because it is too large
Load Diff
188
arch/arm/dts/imx6sx-sabreauto.dts
Normal file
188
arch/arm/dts/imx6sx-sabreauto.dts
Normal file
@ -0,0 +1,188 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "imx6sx.dtsi"
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/ {
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model = "Freescale i.MX6 SoloX Sabre Auto Board";
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compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
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memory {
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reg = <0x80000000 0x80000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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vcc_sd3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_vcc_sd3>;
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regulator-name = "VCC_SD3";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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keep-power-in-suspend;
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wakeup-source;
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vmmc-supply = <&vcc_sd3>;
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status = "okay";
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};
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&usdhc4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4>;
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bus-width = <8>;
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cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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keep-power-in-suspend;
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wakeup-source;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_1>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3_2>;
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status = "okay";
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max7310_a: gpio@30 {
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compatible = "maxim,max7310";
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reg = <0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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max7310_b: gpio@32 {
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compatible = "maxim,max7310";
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reg = <0x32>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&iomuxc {
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imx6x-sabreauto {
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pinctrl_i2c2_1: i2c2grp-1 {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
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MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
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>;
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};
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pinctrl_i2c3_2: i2c3grp-2 {
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fsl,pins = <
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MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
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MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
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>;
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};
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pinctrl_uart1: uart1grp {
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||||||
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
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MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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||||||
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fsl,pins = <
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MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
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||||||
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MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
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MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
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MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
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MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
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MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
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||||||
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MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
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||||||
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MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
|
||||||
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MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
|
||||||
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MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
|
||||||
|
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
|
||||||
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MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
|
||||||
|
>;
|
||||||
|
};
|
||||||
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|
||||||
|
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
||||||
|
fsl,pins = <
|
||||||
|
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
|
||||||
|
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
|
||||||
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MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
|
||||||
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MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
|
||||||
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MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
|
||||||
|
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
|
||||||
|
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
|
||||||
|
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
|
||||||
|
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
|
||||||
|
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
||||||
|
fsl,pins = <
|
||||||
|
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
|
||||||
|
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
|
||||||
|
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
|
||||||
|
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_usdhc4: usdhc4grp {
|
||||||
|
fsl,pins = <
|
||||||
|
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
|
||||||
|
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
|
||||||
|
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
|
||||||
|
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
|
||||||
|
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
|
||||||
|
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
|
||||||
|
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
|
||||||
|
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_vcc_sd3: vccsd3grp {
|
||||||
|
fsl,pins = <
|
||||||
|
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
1298
arch/arm/dts/imx6sx.dtsi
Normal file
1298
arch/arm/dts/imx6sx.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@ -27,8 +27,7 @@ u32 spl_boot_device(void)
|
|||||||
* Check for BMODE if serial downloader is enabled
|
* Check for BMODE if serial downloader is enabled
|
||||||
* BOOT_MODE - see IMX6DQRM Table 8-1
|
* BOOT_MODE - see IMX6DQRM Table 8-1
|
||||||
*/
|
*/
|
||||||
if ((((bmode >> 24) & 0x03) == 0x01) || /* Serial Downloader */
|
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
|
||||||
(gpr10_boot && (reg == 1)))
|
|
||||||
return BOOT_DEVICE_UART;
|
return BOOT_DEVICE_UART;
|
||||||
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
|
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
|
||||||
switch ((reg & 0x000000FF) >> 4) {
|
switch ((reg & 0x000000FF) >> 4) {
|
||||||
@ -40,6 +39,9 @@ u32 spl_boot_device(void)
|
|||||||
else
|
else
|
||||||
return BOOT_DEVICE_NOR;
|
return BOOT_DEVICE_NOR;
|
||||||
break;
|
break;
|
||||||
|
/* Reserved: Used to force Serial Downloader */
|
||||||
|
case 0x1:
|
||||||
|
return BOOT_DEVICE_UART;
|
||||||
/* SATA: See 8.5.4, Table 8-20 */
|
/* SATA: See 8.5.4, Table 8-20 */
|
||||||
case 0x2:
|
case 0x2:
|
||||||
return BOOT_DEVICE_SATA;
|
return BOOT_DEVICE_SATA;
|
||||||
|
|||||||
@ -4,8 +4,8 @@
|
|||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_MACH_LITESOM_SOM_H__
|
#ifndef __ARCH_ARM_MX6UL_LITESOM_H__
|
||||||
#define __ARCH_ARM_MACH_LITESOM_SOM_H__
|
#define __ARCH_ARM_MX6UL_LITESOM_H__
|
||||||
|
|
||||||
int litesom_mmc_init(bd_t *bis);
|
int litesom_mmc_init(bd_t *bis);
|
||||||
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
config LITESOM
|
|
||||||
bool
|
|
||||||
select MX6UL
|
|
||||||
select DM
|
|
||||||
select DM_THERMAL
|
|
||||||
select SUPPORT_SPL
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
# (C) Copyright 2016 Grinn
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y := litesom.o
|
|
||||||
@ -16,12 +16,9 @@
|
|||||||
#include <asm/imx-common/iomux-v3.h>
|
#include <asm/imx-common/iomux-v3.h>
|
||||||
#include <asm/imx-common/boot_mode.h>
|
#include <asm/imx-common/boot_mode.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/imx-common/mxc_i2c.h>
|
|
||||||
#include <linux/sizes.h>
|
#include <linux/sizes.h>
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <fsl_esdhc.h>
|
#include <fsl_esdhc.h>
|
||||||
#include <mmc.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
#include <netdev.h>
|
#include <netdev.h>
|
||||||
#include <power/pmic.h>
|
#include <power/pmic.h>
|
||||||
@ -37,15 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||||
|
|
||||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
||||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
|
||||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
||||||
|
|
||||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
||||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
|
||||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
|
||||||
PAD_CTL_ODE)
|
|
||||||
|
|
||||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||||
PAD_CTL_SPEED_HIGH | \
|
PAD_CTL_SPEED_HIGH | \
|
||||||
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
|
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
|
||||||
@ -56,54 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||||
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
|
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
|
||||||
|
|
||||||
#define I2C_PMIC 1
|
|
||||||
|
|
||||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||||
PAD_CTL_SRE_FAST)
|
PAD_CTL_SRE_FAST)
|
||||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||||
|
|
||||||
/*Define for building port exp gpio, pin starts from 0*/
|
|
||||||
#define PORTEXP_IO_NR(chip, pin) \
|
|
||||||
((chip << 5) + pin)
|
|
||||||
|
|
||||||
/*Get the chip addr from a ioexp gpio*/
|
|
||||||
#define PORTEXP_IO_TO_CHIP(gpio_nr) \
|
|
||||||
(gpio_nr >> 5)
|
|
||||||
|
|
||||||
/*Get the pin number from a ioexp gpio*/
|
|
||||||
#define PORTEXP_IO_TO_PIN(gpio_nr) \
|
|
||||||
(gpio_nr & 0x1f)
|
|
||||||
|
|
||||||
#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
|
|
||||||
#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
|
|
||||||
|
|
||||||
static int port_exp_direction_output(unsigned gpio, int value)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
i2c_set_bus_num(2);
|
|
||||||
ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
|
|
||||||
(1 << PORTEXP_IO_TO_PIN(gpio)),
|
|
||||||
(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
|
|
||||||
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
|
|
||||||
(1 << PORTEXP_IO_TO_PIN(gpio)),
|
|
||||||
(value << PORTEXP_IO_TO_PIN(gpio)));
|
|
||||||
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int dram_init(void)
|
int dram_init(void)
|
||||||
{
|
{
|
||||||
gd->ram_size = imx_ddr_size();
|
gd->ram_size = imx_ddr_size();
|
||||||
@ -116,41 +61,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
|
|||||||
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
};
|
};
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
|
||||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
|
|
||||||
/* CD pin */
|
|
||||||
MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
|
|
||||||
/* RST_B, used for power reset cycle */
|
|
||||||
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
|
||||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
|
|
||||||
/* CD pin */
|
|
||||||
MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
static iomux_v3_cfg_t const fec2_pads[] = {
|
static iomux_v3_cfg_t const fec2_pads[] = {
|
||||||
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||||
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||||
@ -217,42 +127,43 @@ int board_phy_config(struct phy_device *phydev)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
|
||||||
/* I2C2 for PMIC */
|
|
||||||
struct i2c_pads_info i2c_pad_info2 = {
|
|
||||||
.scl = {
|
|
||||||
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
|
|
||||||
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
|
|
||||||
.gp = IMX_GPIO_NR(1, 2),
|
|
||||||
},
|
|
||||||
.sda = {
|
|
||||||
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
|
|
||||||
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
|
|
||||||
.gp = IMX_GPIO_NR(1, 3),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
/* I2C3 for IO Expander */
|
|
||||||
struct i2c_pads_info i2c_pad_info3 = {
|
|
||||||
.scl = {
|
|
||||||
.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
|
|
||||||
.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
|
|
||||||
.gp = IMX_GPIO_NR(2, 14),
|
|
||||||
},
|
|
||||||
.sda = {
|
|
||||||
.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
|
|
||||||
.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
|
|
||||||
.gp = IMX_GPIO_NR(2, 19),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
int power_init_board(void)
|
int power_init_board(void)
|
||||||
{
|
{
|
||||||
struct pmic *p;
|
struct udevice *dev;
|
||||||
|
int ret;
|
||||||
|
u32 dev_id, rev_id, i;
|
||||||
|
u32 switch_num = 6;
|
||||||
|
u32 offset = PFUZE100_SW1CMODE;
|
||||||
|
|
||||||
p = pfuze_common_init(I2C_PMIC);
|
ret = pmic_get("pfuze100", &dev);
|
||||||
if (!p)
|
if (ret == -ENODEV)
|
||||||
return -ENODEV;
|
return 0;
|
||||||
|
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
|
||||||
|
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
|
||||||
|
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
||||||
|
|
||||||
|
|
||||||
|
/* Init mode to APS_PFM */
|
||||||
|
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
|
||||||
|
|
||||||
|
for (i = 0; i < switch_num - 1; i++)
|
||||||
|
pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
|
||||||
|
|
||||||
|
/* set SW1AB staby volatage 0.975V */
|
||||||
|
pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
|
||||||
|
|
||||||
|
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||||
|
pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
|
||||||
|
|
||||||
|
/* set SW1C staby volatage 1.10V */
|
||||||
|
pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
|
||||||
|
|
||||||
|
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
||||||
|
pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -307,78 +218,6 @@ int board_early_init_f(void)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
|
||||||
{USDHC3_BASE_ADDR},
|
|
||||||
{USDHC4_BASE_ADDR},
|
|
||||||
};
|
|
||||||
|
|
||||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
|
|
||||||
#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
|
|
||||||
#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
|
|
||||||
|
|
||||||
int board_mmc_getcd(struct mmc *mmc)
|
|
||||||
{
|
|
||||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
||||||
int ret = 0;
|
|
||||||
|
|
||||||
switch (cfg->esdhc_base) {
|
|
||||||
case USDHC3_BASE_ADDR:
|
|
||||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
|
||||||
break;
|
|
||||||
case USDHC4_BASE_ADDR:
|
|
||||||
ret = !gpio_get_value(USDHC4_CD_GPIO);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_mmc_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
int i, ret;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* According to the board_mmc_init() the following map is done:
|
|
||||||
* (U-Boot device node) (Physical Port)
|
|
||||||
* mmc0 USDHC3
|
|
||||||
* mmc1 USDHC4
|
|
||||||
*/
|
|
||||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
||||||
switch (i) {
|
|
||||||
case 0:
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
|
||||||
gpio_direction_input(USDHC3_CD_GPIO);
|
|
||||||
|
|
||||||
/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
|
|
||||||
gpio_direction_output(USDHC3_RST_GPIO, 0);
|
|
||||||
udelay(1000); /* need 1ms at least */
|
|
||||||
gpio_direction_output(USDHC3_RST_GPIO, 1);
|
|
||||||
|
|
||||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
|
||||||
gpio_direction_input(USDHC4_CD_GPIO);
|
|
||||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printf("Warning: you configured more USDHC controllers"
|
|
||||||
"(%d) than supported by the board\n", i + 1);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
||||||
if (ret) {
|
|
||||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_QSPI
|
#ifdef CONFIG_FSL_QSPI
|
||||||
|
|
||||||
#define QSPI_PAD_CTRL1 \
|
#define QSPI_PAD_CTRL1 \
|
||||||
@ -450,21 +289,36 @@ static void setup_gpmi_nand(void)
|
|||||||
|
|
||||||
int board_init(void)
|
int board_init(void)
|
||||||
{
|
{
|
||||||
|
struct gpio_desc desc;
|
||||||
|
int ret;
|
||||||
|
|
||||||
/* Address of boot parameters */
|
/* Address of boot parameters */
|
||||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_I2C_MXC
|
ret = dm_gpio_lookup_name("gpio@30_4", &desc);
|
||||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
if (ret)
|
||||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
|
return ret;
|
||||||
#endif
|
|
||||||
|
|
||||||
|
ret = dm_gpio_request(&desc, "cpu_per_rst_b");
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
|
/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
|
||||||
port_exp_direction_output(CPU_PER_RST_B, 0);
|
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
|
||||||
udelay(500);
|
udelay(500);
|
||||||
port_exp_direction_output(CPU_PER_RST_B, 1);
|
dm_gpio_set_value(&desc, 1);
|
||||||
|
|
||||||
|
ret = dm_gpio_lookup_name("gpio@32_2", &desc);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = dm_gpio_request(&desc, "steer_enet");
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
|
||||||
|
udelay(500);
|
||||||
/* Set steering signal to L for selecting B0 */
|
/* Set steering signal to L for selecting B0 */
|
||||||
port_exp_direction_output(STEER_ENET, 0);
|
dm_gpio_set_value(&desc, 0);
|
||||||
|
|
||||||
#ifdef CONFIG_USB_EHCI_MX6
|
#ifdef CONFIG_USB_EHCI_MX6
|
||||||
setup_usb();
|
setup_usb();
|
||||||
|
|||||||
@ -9,6 +9,7 @@
|
|||||||
#include <asm/arch/iomux.h>
|
#include <asm/arch/iomux.h>
|
||||||
#include <asm/arch/imx-regs.h>
|
#include <asm/arch/imx-regs.h>
|
||||||
#include <asm/arch/crm_regs.h>
|
#include <asm/arch/crm_regs.h>
|
||||||
|
#include <asm/arch/litesom.h>
|
||||||
#include <asm/arch/mx6ul_pins.h>
|
#include <asm/arch/mx6ul_pins.h>
|
||||||
#include <asm/arch/mx6-pins.h>
|
#include <asm/arch/mx6-pins.h>
|
||||||
#include <asm/arch/sys_proto.h>
|
#include <asm/arch/sys_proto.h>
|
||||||
@ -20,7 +21,6 @@
|
|||||||
#include <fsl_esdhc.h>
|
#include <fsl_esdhc.h>
|
||||||
#include <linux/sizes.h>
|
#include <linux/sizes.h>
|
||||||
#include <linux/fb.h>
|
#include <linux/fb.h>
|
||||||
#include <mach/litesom.h>
|
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
#include <mmc.h>
|
#include <mmc.h>
|
||||||
#include <netdev.h>
|
#include <netdev.h>
|
||||||
|
|||||||
12
board/liebherr/mccmon6/Kconfig
Normal file
12
board/liebherr/mccmon6/Kconfig
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
if TARGET_MCCMON6
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "mccmon6"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "liebherr"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "mccmon6"
|
||||||
|
|
||||||
|
endif
|
||||||
7
board/liebherr/mccmon6/MAINTAINERS
Normal file
7
board/liebherr/mccmon6/MAINTAINERS
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
MCCMON6 BOARD
|
||||||
|
M: Lukasz Majewski <lukma@denx.de>
|
||||||
|
S: Maintained
|
||||||
|
F: board/liebherr/mccmon6/
|
||||||
|
F: include/configs/mccmon6.h
|
||||||
|
F: configs/mccmon6_nor_defconfig
|
||||||
|
F: configs/mccmon6_sd_defconfig
|
||||||
8
board/liebherr/mccmon6/Makefile
Normal file
8
board/liebherr/mccmon6/Makefile
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
#
|
||||||
|
# (C) Copyright 2016-2017
|
||||||
|
# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y := mccmon6.o spl.o
|
||||||
490
board/liebherr/mccmon6/mccmon6.c
Normal file
490
board/liebherr/mccmon6/mccmon6.c
Normal file
@ -0,0 +1,490 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016-2017
|
||||||
|
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/arch/clock.h>
|
||||||
|
#include <asm/arch/iomux.h>
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
#include <asm/arch/mx6-pins.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <asm/gpio.h>
|
||||||
|
#include <asm/imx-common/iomux-v3.h>
|
||||||
|
#include <asm/imx-common/mxc_i2c.h>
|
||||||
|
#include <asm/imx-common/spi.h>
|
||||||
|
#include <asm/imx-common/boot_mode.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <fsl_esdhc.h>
|
||||||
|
#include <mmc.h>
|
||||||
|
#include <netdev.h>
|
||||||
|
#include <micrel.h>
|
||||||
|
#include <phy.h>
|
||||||
|
#include <input.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include <spl.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||||
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||||
|
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||||
|
|
||||||
|
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
|
||||||
|
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
||||||
|
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||||
|
|
||||||
|
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||||
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||||
|
|
||||||
|
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
|
||||||
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||||
|
|
||||||
|
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||||
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||||
|
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||||
|
|
||||||
|
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||||
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||||
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||||
|
|
||||||
|
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
|
||||||
|
#define ETH_PHY_RESET IMX_GPIO_NR(1, 27)
|
||||||
|
#define ECSPI3_CS0 IMX_GPIO_NR(4, 24)
|
||||||
|
#define ECSPI3_FLWP IMX_GPIO_NR(4, 27)
|
||||||
|
#define NOR_WP IMX_GPIO_NR(1, 1)
|
||||||
|
#define DISPLAY_EN IMX_GPIO_NR(1, 2)
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
gd->ram_size = imx_ddr_size();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||||
|
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||||
|
};
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||||
|
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
/* Carrier MicroSD Card Detect */
|
||||||
|
IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
};
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||||
|
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||||
|
};
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const enet_pads[] = {
|
||||||
|
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
|
||||||
|
| MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
|
||||||
|
| MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
|
||||||
|
| MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||||
|
/* KSZ9031 PHY Reset */
|
||||||
|
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
};
|
||||||
|
|
||||||
|
static void setup_iomux_uart(void)
|
||||||
|
{
|
||||||
|
SETUP_IOMUX_PADS(uart1_pads);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_iomux_enet(void)
|
||||||
|
{
|
||||||
|
SETUP_IOMUX_PADS(enet_pads);
|
||||||
|
|
||||||
|
/* Reset KSZ9031 PHY */
|
||||||
|
gpio_direction_output(ETH_PHY_RESET, 0);
|
||||||
|
mdelay(10);
|
||||||
|
gpio_set_value(ETH_PHY_RESET, 1);
|
||||||
|
udelay(100);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||||
|
{USDHC3_BASE_ADDR},
|
||||||
|
{USDHC2_BASE_ADDR},
|
||||||
|
};
|
||||||
|
|
||||||
|
int board_mmc_getcd(struct mmc *mmc)
|
||||||
|
{
|
||||||
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
switch (cfg->esdhc_base) {
|
||||||
|
case USDHC2_BASE_ADDR:
|
||||||
|
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||||
|
break;
|
||||||
|
case USDHC3_BASE_ADDR:
|
||||||
|
/*
|
||||||
|
* eMMC don't have card detect pin - since it is soldered to the
|
||||||
|
* PCB board
|
||||||
|
*/
|
||||||
|
ret = 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_mmc_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u32 index = 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC MAP
|
||||||
|
* (U-Boot device node) (Physical Port)
|
||||||
|
* mmc0 Soldered on board eMMC device
|
||||||
|
* mmc1 MicroSD card
|
||||||
|
*/
|
||||||
|
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||||
|
switch (index) {
|
||||||
|
case 0:
|
||||||
|
SETUP_IOMUX_PADS(usdhc3_pads);
|
||||||
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||||
|
usdhc_cfg[0].max_bus_width = 8;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
SETUP_IOMUX_PADS(usdhc2_pads);
|
||||||
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||||
|
usdhc_cfg[1].max_bus_width = 4;
|
||||||
|
gpio_direction_input(USDHC2_CD_GPIO);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
|
||||||
|
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const eimnor_pads[] = {
|
||||||
|
IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
};
|
||||||
|
|
||||||
|
static void eimnor_cs_setup(void)
|
||||||
|
{
|
||||||
|
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
|
||||||
|
|
||||||
|
|
||||||
|
/* NOR configuration */
|
||||||
|
writel(0x00620181, &weim_regs->cs0gcr1);
|
||||||
|
writel(0x00000001, &weim_regs->cs0gcr2);
|
||||||
|
writel(0x0b020000, &weim_regs->cs0rcr1);
|
||||||
|
writel(0x0000b000, &weim_regs->cs0rcr2);
|
||||||
|
writel(0x0804a240, &weim_regs->cs0wcr1);
|
||||||
|
writel(0x00000000, &weim_regs->cs0wcr2);
|
||||||
|
|
||||||
|
writel(0x00000120, &weim_regs->wcr);
|
||||||
|
writel(0x00000010, &weim_regs->wiar);
|
||||||
|
writel(0x00000000, &weim_regs->ear);
|
||||||
|
|
||||||
|
set_chipselect_size(CS0_128);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_eimnor(void)
|
||||||
|
{
|
||||||
|
SETUP_IOMUX_PADS(eimnor_pads);
|
||||||
|
gpio_direction_output(NOR_WP, 1);
|
||||||
|
|
||||||
|
enable_eim_clk(1);
|
||||||
|
eimnor_cs_setup();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* mccmon6 board has SPI Flash is connected to SPI3 */
|
||||||
|
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||||
|
{
|
||||||
|
return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const ecspi3_pads[] = {
|
||||||
|
/* SPI3 */
|
||||||
|
IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||||
|
IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||||
|
};
|
||||||
|
|
||||||
|
void setup_spi(void)
|
||||||
|
{
|
||||||
|
SETUP_IOMUX_PADS(ecspi3_pads);
|
||||||
|
|
||||||
|
enable_spi_clk(true, 2);
|
||||||
|
|
||||||
|
/* set cs0 to high */
|
||||||
|
gpio_direction_output(ECSPI3_CS0, 1);
|
||||||
|
|
||||||
|
/* set flwp to high */
|
||||||
|
gpio_direction_output(ECSPI3_FLWP, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
struct i2c_pads_info mx6q_i2c1_pad_info = {
|
||||||
|
.scl = {
|
||||||
|
.i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gp = IMX_GPIO_NR(5, 27)
|
||||||
|
},
|
||||||
|
.sda = {
|
||||||
|
.i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gp = IMX_GPIO_NR(5, 26)
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
struct i2c_pads_info mx6q_i2c2_pad_info = {
|
||||||
|
.scl = {
|
||||||
|
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gp = IMX_GPIO_NR(4, 12)
|
||||||
|
},
|
||||||
|
.sda = {
|
||||||
|
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
|
||||||
|
| MUX_PAD_CTRL(I2C_PAD_CTRL),
|
||||||
|
.gp = IMX_GPIO_NR(4, 13)
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
int board_eth_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
setup_iomux_enet();
|
||||||
|
|
||||||
|
return cpu_eth_init(bis);
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
setup_iomux_uart();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
/* address of boot parameters */
|
||||||
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||||
|
|
||||||
|
gpio_direction_output(DISPLAY_EN, 1);
|
||||||
|
|
||||||
|
setup_eimnor();
|
||||||
|
setup_spi();
|
||||||
|
|
||||||
|
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
|
||||||
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_late_init(void)
|
||||||
|
{
|
||||||
|
setenv("board_name", "mccmon6");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
puts("Board: MCCMON6\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_phy_config(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Default setting for GMII Clock Pad Skew Register 0x1EF:
|
||||||
|
* MMD Address 0x2h, Register 0x8h
|
||||||
|
*
|
||||||
|
* GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
|
||||||
|
* RX_CLK Pad Skew 0xF -> 0.9 nsec skew
|
||||||
|
*
|
||||||
|
* Adjustment -> write 0x3FF:
|
||||||
|
* GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
|
||||||
|
* RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
ksz9031_phy_extended_write(phydev, 0x2,
|
||||||
|
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
|
||||||
|
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
|
||||||
|
|
||||||
|
ksz9031_phy_extended_write(phydev, 0x02,
|
||||||
|
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
|
||||||
|
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
|
||||||
|
|
||||||
|
ksz9031_phy_extended_write(phydev, 0x2,
|
||||||
|
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
|
||||||
|
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||||
|
0x3333);
|
||||||
|
|
||||||
|
ksz9031_phy_extended_write(phydev, 0x2,
|
||||||
|
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
|
||||||
|
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||||
|
0x2052);
|
||||||
|
|
||||||
|
if (phydev->drv->config)
|
||||||
|
phydev->drv->config(phydev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BOARD_INIT
|
||||||
|
void spl_board_init(void)
|
||||||
|
{
|
||||||
|
setup_eimnor();
|
||||||
|
|
||||||
|
gpio_direction_output(DISPLAY_EN, 1);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_SPL_BOARD_INIT */
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
void board_boot_order(u32 *spl_boot_list)
|
||||||
|
{
|
||||||
|
switch (spl_boot_device()) {
|
||||||
|
case BOOT_DEVICE_MMC2:
|
||||||
|
case BOOT_DEVICE_MMC1:
|
||||||
|
spl_boot_list[0] = BOOT_DEVICE_MMC2;
|
||||||
|
spl_boot_list[1] = BOOT_DEVICE_MMC1;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_NOR:
|
||||||
|
spl_boot_list[0] = BOOT_DEVICE_NOR;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_SPL_BUILD */
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_OS_BOOT
|
||||||
|
int spl_start_uboot(void)
|
||||||
|
{
|
||||||
|
char s[16];
|
||||||
|
int ret;
|
||||||
|
/*
|
||||||
|
* We use BOOT_DEVICE_MMC1, but SD card is connected
|
||||||
|
* to MMC2
|
||||||
|
*
|
||||||
|
* Correct "mapping" is delivered in board defined
|
||||||
|
* board_boot_order() function.
|
||||||
|
*
|
||||||
|
* SD card boot is regarded as a "development" one,
|
||||||
|
* hence we _always_ go through the u-boot.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
if (spl_boot_device() == BOOT_DEVICE_MMC1)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
/* break into full u-boot on 'c' */
|
||||||
|
if (serial_tstc() && serial_getc() == 'c')
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
env_init();
|
||||||
|
ret = getenv_f("boot_os", s, sizeof(s));
|
||||||
|
if ((ret != -1) && (strcmp(s, "no") == 0))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check if SWUpdate recovery needs to be started
|
||||||
|
*
|
||||||
|
* recovery_status = NULL (not set - ret == -1) -> normal operation
|
||||||
|
*
|
||||||
|
* recovery_status = progress or
|
||||||
|
* recovery_status = failed or
|
||||||
|
* recovery_status = <any value> -> start SWUpdate
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
ret = getenv_f("recovery_status", s, sizeof(s));
|
||||||
|
if (ret != -1)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_SPL_OS_BOOT */
|
||||||
9
board/liebherr/mccmon6/mon6_imximage_nor.cfg
Normal file
9
board/liebherr/mccmon6/mon6_imximage_nor.cfg
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016-2017
|
||||||
|
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
IMAGE_VERSION 2
|
||||||
|
BOOT_FROM nor
|
||||||
9
board/liebherr/mccmon6/mon6_imximage_sd.cfg
Normal file
9
board/liebherr/mccmon6/mon6_imximage_sd.cfg
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016-2017
|
||||||
|
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
IMAGE_VERSION 2
|
||||||
|
BOOT_FROM sd
|
||||||
317
board/liebherr/mccmon6/spl.c
Normal file
317
board/liebherr/mccmon6/spl.c
Normal file
@ -0,0 +1,317 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2014 Wandboard
|
||||||
|
* Author: Tungyi Lin <tungyilin1127@gmail.com>
|
||||||
|
* Richard Hu <hakahu@gmail.com>
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/arch/clock.h>
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
#include <asm/arch/iomux.h>
|
||||||
|
#include <asm/arch/mx6-pins.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <asm/gpio.h>
|
||||||
|
#include <asm/imx-common/iomux-v3.h>
|
||||||
|
#include <asm/imx-common/video.h>
|
||||||
|
#include <mmc.h>
|
||||||
|
#include <fsl_esdhc.h>
|
||||||
|
#include <asm/arch/crm_regs.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <spl.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPL_BUILD)
|
||||||
|
#include <asm/arch/mx6-ddr.h>
|
||||||
|
/*
|
||||||
|
* Driving strength:
|
||||||
|
* 0x30 == 40 Ohm
|
||||||
|
* 0x28 == 48 Ohm
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IMX6DQ_DRIVE_STRENGTH 0x30
|
||||||
|
#define IMX6SDL_DRIVE_STRENGTH 0x28
|
||||||
|
|
||||||
|
/* configure MX6Q/DUAL mmdc DDR io registers */
|
||||||
|
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
|
||||||
|
.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_cas = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_ras = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_reset = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdba2 = 0x00000000,
|
||||||
|
.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* configure MX6Q/DUAL mmdc GRP io registers */
|
||||||
|
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
|
||||||
|
.grp_ddr_type = 0x000c0000,
|
||||||
|
.grp_ddrmode_ctl = 0x00020000,
|
||||||
|
.grp_ddrpke = 0x00000000,
|
||||||
|
.grp_addds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_ddrmode = 0x00020000,
|
||||||
|
.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
|
||||||
|
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
|
||||||
|
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdba2 = 0x00000000,
|
||||||
|
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
|
||||||
|
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
|
||||||
|
.grp_ddr_type = 0x000c0000,
|
||||||
|
.grp_ddrmode_ctl = 0x00020000,
|
||||||
|
.grp_ddrpke = 0x00000000,
|
||||||
|
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_ddrmode = 0x00020000,
|
||||||
|
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* H5T04G63AFR-PB */
|
||||||
|
static struct mx6_ddr3_cfg h5t04g63afr = {
|
||||||
|
.mem_speed = 1600,
|
||||||
|
.density = 4,
|
||||||
|
.width = 16,
|
||||||
|
.banks = 8,
|
||||||
|
.rowaddr = 15,
|
||||||
|
.coladdr = 10,
|
||||||
|
.pagesz = 2,
|
||||||
|
.trcd = 1375,
|
||||||
|
.trcmin = 4875,
|
||||||
|
.trasmin = 3500,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* H5TQ2G63DFR-H9 */
|
||||||
|
static struct mx6_ddr3_cfg h5tq2g63dfr = {
|
||||||
|
.mem_speed = 1333,
|
||||||
|
.density = 2,
|
||||||
|
.width = 16,
|
||||||
|
.banks = 8,
|
||||||
|
.rowaddr = 14,
|
||||||
|
.coladdr = 10,
|
||||||
|
.pagesz = 2,
|
||||||
|
.trcd = 1350,
|
||||||
|
.trcmin = 4950,
|
||||||
|
.trasmin = 3600,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
|
||||||
|
.p0_mpwldectrl0 = 0x001f001f,
|
||||||
|
.p0_mpwldectrl1 = 0x001f001f,
|
||||||
|
.p1_mpwldectrl0 = 0x001f001f,
|
||||||
|
.p1_mpwldectrl1 = 0x001f001f,
|
||||||
|
.p0_mpdgctrl0 = 0x4301030d,
|
||||||
|
.p0_mpdgctrl1 = 0x03020277,
|
||||||
|
.p1_mpdgctrl0 = 0x4300030a,
|
||||||
|
.p1_mpdgctrl1 = 0x02780248,
|
||||||
|
.p0_mprddlctl = 0x4536393b,
|
||||||
|
.p1_mprddlctl = 0x36353441,
|
||||||
|
.p0_mpwrdlctl = 0x41414743,
|
||||||
|
.p1_mpwrdlctl = 0x462f453f,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* DDR 64bit 2GB */
|
||||||
|
static struct mx6_ddr_sysinfo mem_q = {
|
||||||
|
.dsize = 2,
|
||||||
|
.cs1_mirror = 0,
|
||||||
|
/* config for full 4GB range so that get_mem_size() works */
|
||||||
|
.cs_density = 32,
|
||||||
|
.ncs = 1,
|
||||||
|
.bi_on = 1,
|
||||||
|
.rtt_nom = 1,
|
||||||
|
.rtt_wr = 0,
|
||||||
|
.ralat = 5,
|
||||||
|
.walat = 0,
|
||||||
|
.mif3_mode = 3,
|
||||||
|
.rst_to_cke = 0x23,
|
||||||
|
.sde_to_rst = 0x10,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
|
||||||
|
.p0_mpwldectrl0 = 0x001f001f,
|
||||||
|
.p0_mpwldectrl1 = 0x001f001f,
|
||||||
|
.p1_mpwldectrl0 = 0x001f001f,
|
||||||
|
.p1_mpwldectrl1 = 0x001f001f,
|
||||||
|
.p0_mpdgctrl0 = 0x420e020e,
|
||||||
|
.p0_mpdgctrl1 = 0x02000200,
|
||||||
|
.p1_mpdgctrl0 = 0x42020202,
|
||||||
|
.p1_mpdgctrl1 = 0x01720172,
|
||||||
|
.p0_mprddlctl = 0x494c4f4c,
|
||||||
|
.p1_mprddlctl = 0x4a4c4c49,
|
||||||
|
.p0_mpwrdlctl = 0x3f3f3133,
|
||||||
|
.p1_mpwrdlctl = 0x39373f2e,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
|
||||||
|
.p0_mpwldectrl0 = 0x0040003c,
|
||||||
|
.p0_mpwldectrl1 = 0x0032003e,
|
||||||
|
.p0_mpdgctrl0 = 0x42350231,
|
||||||
|
.p0_mpdgctrl1 = 0x021a0218,
|
||||||
|
.p0_mprddlctl = 0x4b4b4e49,
|
||||||
|
.p0_mpwrdlctl = 0x3f3f3035,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* DDR 64bit 1GB */
|
||||||
|
static struct mx6_ddr_sysinfo mem_dl = {
|
||||||
|
.dsize = 2,
|
||||||
|
.cs1_mirror = 0,
|
||||||
|
/* config for full 4GB range so that get_mem_size() works */
|
||||||
|
.cs_density = 32,
|
||||||
|
.ncs = 1,
|
||||||
|
.bi_on = 1,
|
||||||
|
.rtt_nom = 1,
|
||||||
|
.rtt_wr = 0,
|
||||||
|
.ralat = 5,
|
||||||
|
.walat = 0,
|
||||||
|
.mif3_mode = 3,
|
||||||
|
.rst_to_cke = 0x23,
|
||||||
|
.sde_to_rst = 0x10,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* DDR 32bit 512MB */
|
||||||
|
static struct mx6_ddr_sysinfo mem_s = {
|
||||||
|
.dsize = 1,
|
||||||
|
.cs1_mirror = 0,
|
||||||
|
/* config for full 4GB range so that get_mem_size() works */
|
||||||
|
.cs_density = 32,
|
||||||
|
.ncs = 1,
|
||||||
|
.bi_on = 1,
|
||||||
|
.rtt_nom = 1,
|
||||||
|
.rtt_wr = 0,
|
||||||
|
.ralat = 5,
|
||||||
|
.walat = 0,
|
||||||
|
.mif3_mode = 3,
|
||||||
|
.rst_to_cke = 0x23,
|
||||||
|
.sde_to_rst = 0x10,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void ccgr_init(void)
|
||||||
|
{
|
||||||
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||||
|
|
||||||
|
writel(0x00C03F3F, &ccm->CCGR0);
|
||||||
|
writel(0x0030FC03, &ccm->CCGR1);
|
||||||
|
writel(0x0FFFC000, &ccm->CCGR2);
|
||||||
|
writel(0x3FF00000, &ccm->CCGR3);
|
||||||
|
writel(0x00FFF300, &ccm->CCGR4);
|
||||||
|
writel(0x0F0000C3, &ccm->CCGR5);
|
||||||
|
writel(0x000003FF, &ccm->CCGR6);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gpr_init(void)
|
||||||
|
{
|
||||||
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||||
|
|
||||||
|
/* enable AXI cache for VDOA/VPU/IPU */
|
||||||
|
writel(0xF00000CF, &iomux->gpr[4]);
|
||||||
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||||
|
writel(0x007F007F, &iomux->gpr[6]);
|
||||||
|
writel(0x007F007F, &iomux->gpr[7]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spl_dram_init(void)
|
||||||
|
{
|
||||||
|
if (is_cpu_type(MXC_CPU_MX6SOLO)) {
|
||||||
|
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
||||||
|
mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
|
||||||
|
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
|
||||||
|
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
||||||
|
mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
|
||||||
|
} else if (is_cpu_type(MXC_CPU_MX6Q)) {
|
||||||
|
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
|
||||||
|
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
|
||||||
|
}
|
||||||
|
|
||||||
|
udelay(100);
|
||||||
|
}
|
||||||
|
|
||||||
|
void board_init_f(ulong dummy)
|
||||||
|
{
|
||||||
|
ccgr_init();
|
||||||
|
|
||||||
|
/* setup AIPS and disable watchdog */
|
||||||
|
arch_cpu_init();
|
||||||
|
|
||||||
|
gpr_init();
|
||||||
|
|
||||||
|
/* iomux */
|
||||||
|
board_early_init_f();
|
||||||
|
|
||||||
|
/* setup GP timer */
|
||||||
|
timer_init();
|
||||||
|
|
||||||
|
/* UART clocks enabled and gd valid - init serial console */
|
||||||
|
preloader_console_init();
|
||||||
|
|
||||||
|
/* DDR initialization */
|
||||||
|
spl_dram_init();
|
||||||
|
|
||||||
|
/* Clear the BSS. */
|
||||||
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||||
|
|
||||||
|
/* load/boot image from boot device */
|
||||||
|
board_init_r(NULL, 0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
33
configs/mccmon6_nor_defconfig
Normal file
33
configs/mccmon6_nor_defconfig
Normal file
@ -0,0 +1,33 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_MX6=y
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_TARGET_MCCMON6=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_NOR_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_BOOTZ=y
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_SF=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_DHCP=y
|
||||||
|
CONFIG_CMD_MII=y
|
||||||
|
CONFIG_CMD_PING=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_EXT2=y
|
||||||
|
CONFIG_CMD_EXT4=y
|
||||||
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
CONFIG_DM_THERMAL=y
|
||||||
|
CONFIG_OF_LIBFDT=y
|
||||||
34
configs/mccmon6_sd_defconfig
Normal file
34
configs/mccmon6_sd_defconfig
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_MX6=y
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_TARGET_MCCMON6=y
|
||||||
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_NOR_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_BOOTZ=y
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_SF=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_DHCP=y
|
||||||
|
CONFIG_CMD_MII=y
|
||||||
|
CONFIG_CMD_PING=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_EXT2=y
|
||||||
|
CONFIG_CMD_EXT4=y
|
||||||
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
CONFIG_DM_THERMAL=y
|
||||||
|
CONFIG_OF_LIBFDT=y
|
||||||
@ -1,6 +1,7 @@
|
|||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_MX6=y
|
CONFIG_ARCH_MX6=y
|
||||||
CONFIG_TARGET_MX6SXSABREAUTO=y
|
CONFIG_TARGET_MX6SXSABREAUTO=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
|
||||||
CONFIG_BOOTDELAY=3
|
CONFIG_BOOTDELAY=3
|
||||||
CONFIG_HUSH_PARSER=y
|
CONFIG_HUSH_PARSER=y
|
||||||
@ -18,14 +19,30 @@ CONFIG_CMD_MII=y
|
|||||||
CONFIG_CMD_PING=y
|
CONFIG_CMD_PING=y
|
||||||
CONFIG_CMD_CACHE=y
|
CONFIG_CMD_CACHE=y
|
||||||
CONFIG_CMD_TIME=y
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_REGULATOR=y
|
||||||
CONFIG_CMD_EXT2=y
|
CONFIG_CMD_EXT2=y
|
||||||
CONFIG_CMD_EXT4=y
|
CONFIG_CMD_EXT4=y
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
CONFIG_CMD_FAT=y
|
CONFIG_CMD_FAT=y
|
||||||
CONFIG_CMD_FS_GENERIC=y
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
# CONFIG_BLK is not set
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_DM_PCA953X=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
# CONFIG_DM_MMC_OPS is not set
|
||||||
CONFIG_SPI_FLASH=y
|
CONFIG_SPI_FLASH=y
|
||||||
CONFIG_SPI_FLASH_BAR=y
|
CONFIG_SPI_FLASH_BAR=y
|
||||||
CONFIG_SPI_FLASH_STMICRO=y
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_IMX6=y
|
||||||
|
CONFIG_DM_PMIC=y
|
||||||
|
CONFIG_DM_PMIC_PFUZE100=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||||
|
CONFIG_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
CONFIG_FSL_QSPI=y
|
CONFIG_FSL_QSPI=y
|
||||||
CONFIG_USB=y
|
CONFIG_USB=y
|
||||||
CONFIG_USB_STORAGE=y
|
CONFIG_USB_STORAGE=y
|
||||||
|
|||||||
@ -2,10 +2,9 @@ High Assurance Boot (HAB) for i.MX6 CPUs
|
|||||||
|
|
||||||
To enable the authenticated or encrypted boot mode of U-Boot, it is
|
To enable the authenticated or encrypted boot mode of U-Boot, it is
|
||||||
required to set the proper configuration for the target board. This
|
required to set the proper configuration for the target board. This
|
||||||
is done by adding the following configuration in in the proper config
|
is done by adding the following configuration in the defconfig file:
|
||||||
file (e.g. include/configs/mx6qarm2.h)
|
|
||||||
|
|
||||||
#define CONFIG_SECURE_BOOT
|
CONFIG_SECURE_BOOT=y
|
||||||
|
|
||||||
In addition, the U-Boot image to be programmed into the
|
In addition, the U-Boot image to be programmed into the
|
||||||
boot media needs to be properly constructed, i.e. it must contain a
|
boot media needs to be properly constructed, i.e. it must contain a
|
||||||
|
|||||||
321
include/configs/mccmon6.h
Normal file
321
include/configs/mccmon6.h
Normal file
@ -0,0 +1,321 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016-2017
|
||||||
|
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#include <config_distro_defaults.h>
|
||||||
|
#include "mx6_common.h"
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||||
|
#include "imx6_spl.h"
|
||||||
|
|
||||||
|
#define CONFIG_SPL_BOARD_INIT
|
||||||
|
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||||
|
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
|
||||||
|
#define CONFIG_SPL_OS_BOOT
|
||||||
|
#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
|
||||||
|
#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
|
||||||
|
#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
|
||||||
|
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Below defines are set but NOT really used since we by
|
||||||
|
* design force U-Boot run when we boot in development
|
||||||
|
* mode from SD card (SD2)
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
|
||||||
|
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
|
||||||
|
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
|
||||||
|
|
||||||
|
/* Size of malloc() pool */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
#define CONFIG_BOARD_LATE_INIT
|
||||||
|
|
||||||
|
#define CONFIG_MXC_UART
|
||||||
|
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||||
|
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
|
||||||
|
|
||||||
|
#define CONFIG_MXC_SPI
|
||||||
|
#define CONFIG_SF_DEFAULT_BUS 2
|
||||||
|
#define CONFIG_SF_DEFAULT_CS 0
|
||||||
|
#define CONFIG_SF_DEFAULT_SPEED 25000000
|
||||||
|
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||||
|
|
||||||
|
/* I2C Configs */
|
||||||
|
#define CONFIG_SYS_I2C
|
||||||
|
#define CONFIG_SYS_I2C_MXC
|
||||||
|
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||||
|
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||||
|
#define CONFIG_SYS_I2C_SPEED 100000
|
||||||
|
|
||||||
|
/* MMC Configuration */
|
||||||
|
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||||
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||||
|
|
||||||
|
#undef CONFIG_SYS_NO_FLASH
|
||||||
|
/* NOR 16-bit mode */
|
||||||
|
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
|
||||||
|
#define CONFIG_SYS_FLASH_PROTECTION
|
||||||
|
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||||
|
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
|
||||||
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
|
||||||
|
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
|
||||||
|
#define CONFIG_FLASH_VERIFY
|
||||||
|
|
||||||
|
/* NOR Flash MTD */
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER
|
||||||
|
#define CONFIG_FLASH_CFI_MTD
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
|
||||||
|
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
|
||||||
|
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
|
||||||
|
|
||||||
|
/* MTD support */
|
||||||
|
#define CONFIG_CMD_MTDPARTS
|
||||||
|
#define CONFIG_MTD_DEVICE
|
||||||
|
#define CONFIG_MTD_PARTITIONS
|
||||||
|
|
||||||
|
#define MTDIDS_DEFAULT "nor0=8000000.nor"
|
||||||
|
#define MTDPARTS_DEFAULT \
|
||||||
|
"mtdparts=8000000.nor:" \
|
||||||
|
"32m@0x0(mccmon6-image.nor)," \
|
||||||
|
"256k@0x40000(u-boot-env.nor)," \
|
||||||
|
"1m@0x80000(u-boot.nor)," \
|
||||||
|
"8m@0x180000(kernel.nor)," \
|
||||||
|
"8m@0x980000(swupdate-kernel.nor)," \
|
||||||
|
"8m@0x1180000(swupdate-rootfs.nor)," \
|
||||||
|
"128k@0x1980000(kernel-dtb.nor)," \
|
||||||
|
"128k@0x19C0000(swupdate-kernel-dtb.nor)"
|
||||||
|
|
||||||
|
/* USB Configs */
|
||||||
|
#define CONFIG_USB_EHCI
|
||||||
|
#define CONFIG_USB_EHCI_MX6
|
||||||
|
#define CONFIG_USB_STORAGE
|
||||||
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||||
|
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||||
|
#define CONFIG_MXC_USB_FLAGS 0
|
||||||
|
|
||||||
|
/* Ethernet Configuration */
|
||||||
|
#define CONFIG_FEC_MXC
|
||||||
|
#define CONFIG_MII
|
||||||
|
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||||
|
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||||
|
#define CONFIG_ETHPRIME "FEC"
|
||||||
|
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||||
|
#define CONFIG_PHYLIB
|
||||||
|
#define CONFIG_PHY_MICREL
|
||||||
|
#define CONFIG_PHY_MICREL_KSZ9031
|
||||||
|
|
||||||
|
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"console=ttymxc0,115200\0" \
|
||||||
|
"fdtfile=imx6q-mccmon6.dtb\0" \
|
||||||
|
"fdt_high=0xffffffff\0" \
|
||||||
|
"initrd_high=0xffffffff\0" \
|
||||||
|
"boot_os=yes\0" \
|
||||||
|
"download_kernel=" \
|
||||||
|
"tftpboot ${kernel_addr} ${kernel_file};" \
|
||||||
|
"tftpboot ${fdt_addr} ${fdtfile};\0" \
|
||||||
|
"get_boot_medium=" \
|
||||||
|
"setenv boot_medium nor;" \
|
||||||
|
"setexpr.l _src_sbmr1 *0x020d8004;" \
|
||||||
|
"setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \
|
||||||
|
"if test ${_b_medium} = 40; then " \
|
||||||
|
"setenv boot_medium sdcard;" \
|
||||||
|
"fi\0" \
|
||||||
|
"kernel_file=uImage\0" \
|
||||||
|
"load_kernel=" \
|
||||||
|
"load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
|
||||||
|
"load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
|
||||||
|
"boot_sd=" \
|
||||||
|
"echo '#######################';" \
|
||||||
|
"echo '# Factory SDcard Boot #';" \
|
||||||
|
"echo '#######################';" \
|
||||||
|
"setenv mmcdev 1;" \
|
||||||
|
"setenv mmcfactorydev 0;" \
|
||||||
|
"setenv mmcfactorypart 1;" \
|
||||||
|
"run factory_flash_img;\0" \
|
||||||
|
"boot_nor=" \
|
||||||
|
"setenv kernelnor 0x08180000;" \
|
||||||
|
"setenv dtbnor 0x09980000;" \
|
||||||
|
"setenv bootargs console=${console} quiet " \
|
||||||
|
""MTDPARTS_DEFAULT" " \
|
||||||
|
"root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
|
||||||
|
"cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
|
||||||
|
"bootm ${kernelnor} - ${dtbloadaddr};\0" \
|
||||||
|
"boot_recovery=" \
|
||||||
|
"echo '#######################';" \
|
||||||
|
"echo '# RECOVERY SWU Boot #';" \
|
||||||
|
"echo '#######################';" \
|
||||||
|
"setenv rootfsloadaddr 0x13000000;" \
|
||||||
|
"setenv swukernelnor 0x08980000;" \
|
||||||
|
"setenv swurootfsnor 0x09180000;" \
|
||||||
|
"setenv swudtbnor 0x099A0000;" \
|
||||||
|
"setenv bootargs console=${console} " \
|
||||||
|
""MTDPARTS_DEFAULT" " \
|
||||||
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||||
|
":${hostname}::off root=/dev/ram rw;" \
|
||||||
|
"cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
|
||||||
|
"cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
|
||||||
|
"bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
|
||||||
|
"boot_tftp=" \
|
||||||
|
"echo '#######################';" \
|
||||||
|
"echo '# TFTP Boot #';" \
|
||||||
|
"echo '#######################';" \
|
||||||
|
"if run download_kernel; then " \
|
||||||
|
"setenv bootargs console=${console} " \
|
||||||
|
"root=/dev/mmcblk0p2 rootwait;" \
|
||||||
|
"bootm ${kernel_addr} - ${fdt_addr};" \
|
||||||
|
"fi\0" \
|
||||||
|
"bootcmd=" \
|
||||||
|
"if test -n ${recovery_status}; then " \
|
||||||
|
"run boot_recovery;" \
|
||||||
|
"else " \
|
||||||
|
"if test ! -n ${boot_medium}; then " \
|
||||||
|
"run get_boot_medium;" \
|
||||||
|
"if test ${boot_medium} = sdcard; then " \
|
||||||
|
"run boot_sd;" \
|
||||||
|
"else " \
|
||||||
|
"run boot_nor;" \
|
||||||
|
"fi;" \
|
||||||
|
"else " \
|
||||||
|
"if test ${boot_medium} = tftp; then " \
|
||||||
|
"run boot_tftp;" \
|
||||||
|
"fi;" \
|
||||||
|
"fi;" \
|
||||||
|
"fi\0" \
|
||||||
|
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||||
|
"fdt_addr=0x18000000\0" \
|
||||||
|
"bootdev=1\0" \
|
||||||
|
"bootpart=1\0" \
|
||||||
|
"kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||||
|
"netdev=eth0\0" \
|
||||||
|
"load_addr=0x11000000\0" \
|
||||||
|
"dtbloadaddr=0x12000000\0" \
|
||||||
|
"uboot_file=u-boot.img\0" \
|
||||||
|
"SPL_file=SPL\0" \
|
||||||
|
"load_uboot=tftp ${load_addr} ${uboot_file}\0" \
|
||||||
|
"nor_img_addr=0x11000000\0" \
|
||||||
|
"nor_img_file=core-image-lwn-mccmon6.nor\0" \
|
||||||
|
"emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
|
||||||
|
"nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
|
||||||
|
"nor_img_size=0x02000000\0" \
|
||||||
|
"factory_script_file=factory.scr\0" \
|
||||||
|
"factory_load_script=" \
|
||||||
|
"if test -e mmc ${mmcdev}:${mmcfactorypart} " \
|
||||||
|
"${factory_script_file}; then " \
|
||||||
|
"load mmc ${mmcdev}:${mmcfactorypart} " \
|
||||||
|
"${loadaddr} ${factory_script_file};" \
|
||||||
|
"fi\0" \
|
||||||
|
"factory_script=echo Running factory script from mmc${mmcdev} ...; " \
|
||||||
|
"source ${loadaddr}\0" \
|
||||||
|
"factory_flash_img="\
|
||||||
|
"echo 'Flash mccmon6 with factory images'; " \
|
||||||
|
"if run factory_load_script; then " \
|
||||||
|
"run factory_script;" \
|
||||||
|
"else " \
|
||||||
|
"echo No factory script: ${factory_script_file} found on " \
|
||||||
|
"device ${mmcdev};" \
|
||||||
|
"run factory_nor_img;" \
|
||||||
|
"run factory_eMMC_img;" \
|
||||||
|
"fi\0" \
|
||||||
|
"factory_eMMC_img="\
|
||||||
|
"echo 'Update mccmon6 eMMC image'; " \
|
||||||
|
"if load mmc ${mmcdev}:${mmcfactorypart} " \
|
||||||
|
"${loadaddr} ${emmc_img_file}; then " \
|
||||||
|
"setexpr fw_sz ${filesize} / 0x200;" \
|
||||||
|
"setexpr fw_sz ${fw_sz} + 1;" \
|
||||||
|
"mmc dev ${mmcfactorydev};" \
|
||||||
|
"mmc write ${loadaddr} 0x0 ${fw_sz};" \
|
||||||
|
"fi\0" \
|
||||||
|
"factory_nor_img="\
|
||||||
|
"echo 'Update mccmon6 NOR image'; " \
|
||||||
|
"if load mmc ${mmcdev}:${mmcfactorypart} " \
|
||||||
|
"${nor_img_addr} ${nor_img_file}; then " \
|
||||||
|
"run nor_update;" \
|
||||||
|
"fi\0" \
|
||||||
|
"nor_update=" \
|
||||||
|
"protect off ${nor_bank_start} +${nor_img_size};" \
|
||||||
|
"erase ${nor_bank_start} +${nor_img_size};" \
|
||||||
|
"setexpr nor_img_size ${nor_img_size} / 4; " \
|
||||||
|
"cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
|
||||||
|
"tftp_nor_uboot="\
|
||||||
|
"echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
|
||||||
|
"setenv nor_img_file u-boot.img; " \
|
||||||
|
"setenv nor_img_size 0x80000; " \
|
||||||
|
"setenv nor_bank_start 0x08080000; " \
|
||||||
|
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
|
||||||
|
"run nor_update;" \
|
||||||
|
"fi\0" \
|
||||||
|
"tftp_nor_uImg="\
|
||||||
|
"echo 'Update mccmon6 NOR uImage via TFTP'; " \
|
||||||
|
"setenv nor_img_file uImage; " \
|
||||||
|
"setenv nor_img_size 0x500000; " \
|
||||||
|
"setenv nor_bank_start 0x08180000; " \
|
||||||
|
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
|
||||||
|
"run nor_update;" \
|
||||||
|
"fi\0" \
|
||||||
|
"tftp_nor_img="\
|
||||||
|
"echo 'Update mccmon6 NOR image via TFTP'; " \
|
||||||
|
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
|
||||||
|
"run nor_update;" \
|
||||||
|
"fi\0" \
|
||||||
|
"tftp_nor_SPL="\
|
||||||
|
"if tftp ${load_addr} SPL_padded; then " \
|
||||||
|
"erase 0x08000000 +0x20000;" \
|
||||||
|
"cp.b ${load_addr} 0x08000000 0x20000;" \
|
||||||
|
"fi;\0" \
|
||||||
|
"tftp_sd_SPL="\
|
||||||
|
"if mmc dev 1; then " \
|
||||||
|
"if tftp ${load_addr} ${SPL_file}; then " \
|
||||||
|
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||||
|
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||||
|
"mmc write ${load_addr} 0x2 ${fw_sz};" \
|
||||||
|
"fi;" \
|
||||||
|
"fi;\0" \
|
||||||
|
"tftp_sd_uboot="\
|
||||||
|
"if mmc dev 1; then " \
|
||||||
|
"if run load_uboot; then " \
|
||||||
|
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||||
|
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||||
|
"mmc write ${load_addr} 0x8A ${fw_sz};" \
|
||||||
|
"fi;" \
|
||||||
|
"fi;\0"
|
||||||
|
|
||||||
|
/* Physical Memory Map */
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1
|
||||||
|
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||||
|
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||||
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||||
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||||
|
|
||||||
|
/* Environment organization */
|
||||||
|
#define CONFIG_ENV_SIZE (SZ_128K)
|
||||||
|
|
||||||
|
/* Envs are stored in NOR flash */
|
||||||
|
#define CONFIG_ENV_IS_IN_FLASH
|
||||||
|
#define CONFIG_ENV_SECT_SIZE (SZ_128K)
|
||||||
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||||
|
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000)
|
||||||
|
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H * */
|
||||||
@ -38,6 +38,7 @@
|
|||||||
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
|
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
|
||||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||||
|
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||||
|
|
||||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||||
|
|||||||
@ -114,19 +114,12 @@
|
|||||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
|
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
|
||||||
|
|
||||||
/* I2C Configs */
|
/* I2C Configs */
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_MXC
|
#define CONFIG_SYS_I2C_MXC
|
||||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_I2C_SPEED 100000
|
||||||
|
|
||||||
/* PMIC */
|
|
||||||
#define CONFIG_POWER
|
|
||||||
#define CONFIG_POWER_I2C
|
|
||||||
#define CONFIG_POWER_PFUZE100
|
|
||||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
|
||||||
|
|
||||||
/* NAND flash command */
|
/* NAND flash command */
|
||||||
#define CONFIG_CMD_NAND
|
#define CONFIG_CMD_NAND
|
||||||
#define CONFIG_CMD_NAND_TRIMFFS
|
#define CONFIG_CMD_NAND_TRIMFFS
|
||||||
|
|||||||
@ -136,6 +136,7 @@
|
|||||||
"fdt_addr=0x18000000\0" \
|
"fdt_addr=0x18000000\0" \
|
||||||
"boot_fdt=try\0" \
|
"boot_fdt=try\0" \
|
||||||
"ip_dyn=yes\0" \
|
"ip_dyn=yes\0" \
|
||||||
|
"usb_pgood_delay=2000\0" \
|
||||||
"mmcdevs=0 1\0" \
|
"mmcdevs=0 1\0" \
|
||||||
"mmcpart=1\0" \
|
"mmcpart=1\0" \
|
||||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||||
@ -205,6 +206,7 @@
|
|||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"bootdevs=" CONFIG_DRIVE_TYPES "\0" \
|
"bootdevs=" CONFIG_DRIVE_TYPES "\0" \
|
||||||
"umsdevs=" CONFIG_UMSDEVS "\0" \
|
"umsdevs=" CONFIG_UMSDEVS "\0" \
|
||||||
|
"usb_pgood_delay=2000\0" \
|
||||||
"console=ttymxc1\0" \
|
"console=ttymxc1\0" \
|
||||||
"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
|
"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
|
||||||
"sf erase 0xc0000 0x2000 && " \
|
"sf erase 0xc0000 0x2000 && " \
|
||||||
|
|||||||
@ -34,6 +34,7 @@
|
|||||||
"initrd_high=0xffffffff\0" \
|
"initrd_high=0xffffffff\0" \
|
||||||
"fdtfile=undefined\0" \
|
"fdtfile=undefined\0" \
|
||||||
"fdt_addr=0x83000000\0" \
|
"fdt_addr=0x83000000\0" \
|
||||||
|
"fdt_addr_r=0x83000000\0" \
|
||||||
"ip_dyn=yes\0" \
|
"ip_dyn=yes\0" \
|
||||||
"mmcdev=0\0" \
|
"mmcdev=0\0" \
|
||||||
"mmcrootfstype=ext4\0" \
|
"mmcrootfstype=ext4\0" \
|
||||||
@ -47,11 +48,10 @@
|
|||||||
"if test $board_name = EXTENDED; then " \
|
"if test $board_name = EXTENDED; then " \
|
||||||
"setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
|
"setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
|
||||||
"if test $fdtfile = UNDEFINED; then " \
|
"if test $fdtfile = UNDEFINED; then " \
|
||||||
"echo WARNING: Could not determine dtb to use; fi; \0" \
|
"echo WARNING: Could not determine dtb to use; fi\0" \
|
||||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||||
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||||
"ramdisk_addr_r=0x83000000\0" \
|
"ramdisk_addr_r=0x83000000\0" \
|
||||||
"ramdiskaddr=0x83000000\0" \
|
|
||||||
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
|
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||||
BOOTENV
|
BOOTENV
|
||||||
|
|
||||||
|
|||||||
280
include/dt-bindings/clock/imx6sx-clock.h
Normal file
280
include/dt-bindings/clock/imx6sx-clock.h
Normal file
@ -0,0 +1,280 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
|
||||||
|
#define __DT_BINDINGS_CLOCK_IMX6SX_H
|
||||||
|
|
||||||
|
#define IMX6SX_CLK_DUMMY 0
|
||||||
|
#define IMX6SX_CLK_CKIL 1
|
||||||
|
#define IMX6SX_CLK_CKIH 2
|
||||||
|
#define IMX6SX_CLK_OSC 3
|
||||||
|
#define IMX6SX_CLK_PLL1_SYS 4
|
||||||
|
#define IMX6SX_CLK_PLL2_BUS 5
|
||||||
|
#define IMX6SX_CLK_PLL3_USB_OTG 6
|
||||||
|
#define IMX6SX_CLK_PLL4_AUDIO 7
|
||||||
|
#define IMX6SX_CLK_PLL5_VIDEO 8
|
||||||
|
#define IMX6SX_CLK_PLL6_ENET 9
|
||||||
|
#define IMX6SX_CLK_PLL7_USB_HOST 10
|
||||||
|
#define IMX6SX_CLK_USBPHY1 11
|
||||||
|
#define IMX6SX_CLK_USBPHY2 12
|
||||||
|
#define IMX6SX_CLK_USBPHY1_GATE 13
|
||||||
|
#define IMX6SX_CLK_USBPHY2_GATE 14
|
||||||
|
#define IMX6SX_CLK_PCIE_REF 15
|
||||||
|
#define IMX6SX_CLK_PCIE_REF_125M 16
|
||||||
|
#define IMX6SX_CLK_ENET_REF 17
|
||||||
|
#define IMX6SX_CLK_PLL2_PFD0 18
|
||||||
|
#define IMX6SX_CLK_PLL2_PFD1 19
|
||||||
|
#define IMX6SX_CLK_PLL2_PFD2 20
|
||||||
|
#define IMX6SX_CLK_PLL2_PFD3 21
|
||||||
|
#define IMX6SX_CLK_PLL3_PFD0 22
|
||||||
|
#define IMX6SX_CLK_PLL3_PFD1 23
|
||||||
|
#define IMX6SX_CLK_PLL3_PFD2 24
|
||||||
|
#define IMX6SX_CLK_PLL3_PFD3 25
|
||||||
|
#define IMX6SX_CLK_PLL2_198M 26
|
||||||
|
#define IMX6SX_CLK_PLL3_120M 27
|
||||||
|
#define IMX6SX_CLK_PLL3_80M 28
|
||||||
|
#define IMX6SX_CLK_PLL3_60M 29
|
||||||
|
#define IMX6SX_CLK_TWD 30
|
||||||
|
#define IMX6SX_CLK_PLL4_POST_DIV 31
|
||||||
|
#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
|
||||||
|
#define IMX6SX_CLK_PLL5_POST_DIV 33
|
||||||
|
#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
|
||||||
|
#define IMX6SX_CLK_STEP 35
|
||||||
|
#define IMX6SX_CLK_PLL1_SW 36
|
||||||
|
#define IMX6SX_CLK_OCRAM_SEL 37
|
||||||
|
#define IMX6SX_CLK_PERIPH_PRE 38
|
||||||
|
#define IMX6SX_CLK_PERIPH2_PRE 39
|
||||||
|
#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
|
||||||
|
#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
|
||||||
|
#define IMX6SX_CLK_PCIE_AXI_SEL 42
|
||||||
|
#define IMX6SX_CLK_GPU_AXI_SEL 43
|
||||||
|
#define IMX6SX_CLK_GPU_CORE_SEL 44
|
||||||
|
#define IMX6SX_CLK_EIM_SLOW_SEL 45
|
||||||
|
#define IMX6SX_CLK_USDHC1_SEL 46
|
||||||
|
#define IMX6SX_CLK_USDHC2_SEL 47
|
||||||
|
#define IMX6SX_CLK_USDHC3_SEL 48
|
||||||
|
#define IMX6SX_CLK_USDHC4_SEL 49
|
||||||
|
#define IMX6SX_CLK_SSI1_SEL 50
|
||||||
|
#define IMX6SX_CLK_SSI2_SEL 51
|
||||||
|
#define IMX6SX_CLK_SSI3_SEL 52
|
||||||
|
#define IMX6SX_CLK_QSPI1_SEL 53
|
||||||
|
#define IMX6SX_CLK_PERCLK_SEL 54
|
||||||
|
#define IMX6SX_CLK_VID_SEL 55
|
||||||
|
#define IMX6SX_CLK_ESAI_SEL 56
|
||||||
|
#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
|
||||||
|
#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
|
||||||
|
#define IMX6SX_CLK_CAN_SEL 59
|
||||||
|
#define IMX6SX_CLK_UART_SEL 60
|
||||||
|
#define IMX6SX_CLK_QSPI2_SEL 61
|
||||||
|
#define IMX6SX_CLK_LDB_DI1_SEL 62
|
||||||
|
#define IMX6SX_CLK_LDB_DI0_SEL 63
|
||||||
|
#define IMX6SX_CLK_SPDIF_SEL 64
|
||||||
|
#define IMX6SX_CLK_AUDIO_SEL 65
|
||||||
|
#define IMX6SX_CLK_ENET_PRE_SEL 66
|
||||||
|
#define IMX6SX_CLK_ENET_SEL 67
|
||||||
|
#define IMX6SX_CLK_M4_PRE_SEL 68
|
||||||
|
#define IMX6SX_CLK_M4_SEL 69
|
||||||
|
#define IMX6SX_CLK_ECSPI_SEL 70
|
||||||
|
#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
|
||||||
|
#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
|
||||||
|
#define IMX6SX_CLK_LCDIF1_SEL 73
|
||||||
|
#define IMX6SX_CLK_LCDIF2_SEL 74
|
||||||
|
#define IMX6SX_CLK_DISPLAY_SEL 75
|
||||||
|
#define IMX6SX_CLK_CSI_SEL 76
|
||||||
|
#define IMX6SX_CLK_CKO1_SEL 77
|
||||||
|
#define IMX6SX_CLK_CKO2_SEL 78
|
||||||
|
#define IMX6SX_CLK_CKO 79
|
||||||
|
#define IMX6SX_CLK_PERIPH_CLK2 80
|
||||||
|
#define IMX6SX_CLK_PERIPH2_CLK2 81
|
||||||
|
#define IMX6SX_CLK_IPG 82
|
||||||
|
#define IMX6SX_CLK_GPU_CORE_PODF 83
|
||||||
|
#define IMX6SX_CLK_GPU_AXI_PODF 84
|
||||||
|
#define IMX6SX_CLK_LCDIF1_PODF 85
|
||||||
|
#define IMX6SX_CLK_QSPI1_PODF 86
|
||||||
|
#define IMX6SX_CLK_EIM_SLOW_PODF 87
|
||||||
|
#define IMX6SX_CLK_LCDIF2_PODF 88
|
||||||
|
#define IMX6SX_CLK_PERCLK 89
|
||||||
|
#define IMX6SX_CLK_VID_PODF 90
|
||||||
|
#define IMX6SX_CLK_CAN_PODF 91
|
||||||
|
#define IMX6SX_CLK_USDHC1_PODF 92
|
||||||
|
#define IMX6SX_CLK_USDHC2_PODF 93
|
||||||
|
#define IMX6SX_CLK_USDHC3_PODF 94
|
||||||
|
#define IMX6SX_CLK_USDHC4_PODF 95
|
||||||
|
#define IMX6SX_CLK_UART_PODF 96
|
||||||
|
#define IMX6SX_CLK_ESAI_PRED 97
|
||||||
|
#define IMX6SX_CLK_ESAI_PODF 98
|
||||||
|
#define IMX6SX_CLK_SSI3_PRED 99
|
||||||
|
#define IMX6SX_CLK_SSI3_PODF 100
|
||||||
|
#define IMX6SX_CLK_SSI1_PRED 101
|
||||||
|
#define IMX6SX_CLK_SSI1_PODF 102
|
||||||
|
#define IMX6SX_CLK_QSPI2_PRED 103
|
||||||
|
#define IMX6SX_CLK_QSPI2_PODF 104
|
||||||
|
#define IMX6SX_CLK_SSI2_PRED 105
|
||||||
|
#define IMX6SX_CLK_SSI2_PODF 106
|
||||||
|
#define IMX6SX_CLK_SPDIF_PRED 107
|
||||||
|
#define IMX6SX_CLK_SPDIF_PODF 108
|
||||||
|
#define IMX6SX_CLK_AUDIO_PRED 109
|
||||||
|
#define IMX6SX_CLK_AUDIO_PODF 110
|
||||||
|
#define IMX6SX_CLK_ENET_PODF 111
|
||||||
|
#define IMX6SX_CLK_M4_PODF 112
|
||||||
|
#define IMX6SX_CLK_ECSPI_PODF 113
|
||||||
|
#define IMX6SX_CLK_LCDIF1_PRED 114
|
||||||
|
#define IMX6SX_CLK_LCDIF2_PRED 115
|
||||||
|
#define IMX6SX_CLK_DISPLAY_PODF 116
|
||||||
|
#define IMX6SX_CLK_CSI_PODF 117
|
||||||
|
#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
|
||||||
|
#define IMX6SX_CLK_LDB_DI0_DIV_7 119
|
||||||
|
#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
|
||||||
|
#define IMX6SX_CLK_LDB_DI1_DIV_7 121
|
||||||
|
#define IMX6SX_CLK_CKO1_PODF 122
|
||||||
|
#define IMX6SX_CLK_CKO2_PODF 123
|
||||||
|
#define IMX6SX_CLK_PERIPH 124
|
||||||
|
#define IMX6SX_CLK_PERIPH2 125
|
||||||
|
#define IMX6SX_CLK_OCRAM 126
|
||||||
|
#define IMX6SX_CLK_AHB 127
|
||||||
|
#define IMX6SX_CLK_MMDC_PODF 128
|
||||||
|
#define IMX6SX_CLK_ARM 129
|
||||||
|
#define IMX6SX_CLK_AIPS_TZ1 130
|
||||||
|
#define IMX6SX_CLK_AIPS_TZ2 131
|
||||||
|
#define IMX6SX_CLK_APBH_DMA 132
|
||||||
|
#define IMX6SX_CLK_ASRC_GATE 133
|
||||||
|
#define IMX6SX_CLK_CAAM_MEM 134
|
||||||
|
#define IMX6SX_CLK_CAAM_ACLK 135
|
||||||
|
#define IMX6SX_CLK_CAAM_IPG 136
|
||||||
|
#define IMX6SX_CLK_CAN1_IPG 137
|
||||||
|
#define IMX6SX_CLK_CAN1_SERIAL 138
|
||||||
|
#define IMX6SX_CLK_CAN2_IPG 139
|
||||||
|
#define IMX6SX_CLK_CAN2_SERIAL 140
|
||||||
|
#define IMX6SX_CLK_CPU_DEBUG 141
|
||||||
|
#define IMX6SX_CLK_DCIC1 142
|
||||||
|
#define IMX6SX_CLK_DCIC2 143
|
||||||
|
#define IMX6SX_CLK_AIPS_TZ3 144
|
||||||
|
#define IMX6SX_CLK_ECSPI1 145
|
||||||
|
#define IMX6SX_CLK_ECSPI2 146
|
||||||
|
#define IMX6SX_CLK_ECSPI3 147
|
||||||
|
#define IMX6SX_CLK_ECSPI4 148
|
||||||
|
#define IMX6SX_CLK_ECSPI5 149
|
||||||
|
#define IMX6SX_CLK_EPIT1 150
|
||||||
|
#define IMX6SX_CLK_EPIT2 151
|
||||||
|
#define IMX6SX_CLK_ESAI_EXTAL 152
|
||||||
|
#define IMX6SX_CLK_WAKEUP 153
|
||||||
|
#define IMX6SX_CLK_GPT_BUS 154
|
||||||
|
#define IMX6SX_CLK_GPT_SERIAL 155
|
||||||
|
#define IMX6SX_CLK_GPU 156
|
||||||
|
#define IMX6SX_CLK_OCRAM_S 157
|
||||||
|
#define IMX6SX_CLK_CANFD 158
|
||||||
|
#define IMX6SX_CLK_CSI 159
|
||||||
|
#define IMX6SX_CLK_I2C1 160
|
||||||
|
#define IMX6SX_CLK_I2C2 161
|
||||||
|
#define IMX6SX_CLK_I2C3 162
|
||||||
|
#define IMX6SX_CLK_OCOTP 163
|
||||||
|
#define IMX6SX_CLK_IOMUXC 164
|
||||||
|
#define IMX6SX_CLK_IPMUX1 165
|
||||||
|
#define IMX6SX_CLK_IPMUX2 166
|
||||||
|
#define IMX6SX_CLK_IPMUX3 167
|
||||||
|
#define IMX6SX_CLK_TZASC1 168
|
||||||
|
#define IMX6SX_CLK_LCDIF_APB 169
|
||||||
|
#define IMX6SX_CLK_PXP_AXI 170
|
||||||
|
#define IMX6SX_CLK_M4 171
|
||||||
|
#define IMX6SX_CLK_ENET 172
|
||||||
|
#define IMX6SX_CLK_DISPLAY_AXI 173
|
||||||
|
#define IMX6SX_CLK_LCDIF2_PIX 174
|
||||||
|
#define IMX6SX_CLK_LCDIF1_PIX 175
|
||||||
|
#define IMX6SX_CLK_LDB_DI0 176
|
||||||
|
#define IMX6SX_CLK_QSPI1 177
|
||||||
|
#define IMX6SX_CLK_MLB 178
|
||||||
|
#define IMX6SX_CLK_MMDC_P0_FAST 179
|
||||||
|
#define IMX6SX_CLK_MMDC_P0_IPG 180
|
||||||
|
#define IMX6SX_CLK_AXI 181
|
||||||
|
#define IMX6SX_CLK_PCIE_AXI 182
|
||||||
|
#define IMX6SX_CLK_QSPI2 183
|
||||||
|
#define IMX6SX_CLK_PER1_BCH 184
|
||||||
|
#define IMX6SX_CLK_PER2_MAIN 185
|
||||||
|
#define IMX6SX_CLK_PWM1 186
|
||||||
|
#define IMX6SX_CLK_PWM2 187
|
||||||
|
#define IMX6SX_CLK_PWM3 188
|
||||||
|
#define IMX6SX_CLK_PWM4 189
|
||||||
|
#define IMX6SX_CLK_GPMI_BCH_APB 190
|
||||||
|
#define IMX6SX_CLK_GPMI_BCH 191
|
||||||
|
#define IMX6SX_CLK_GPMI_IO 192
|
||||||
|
#define IMX6SX_CLK_GPMI_APB 193
|
||||||
|
#define IMX6SX_CLK_ROM 194
|
||||||
|
#define IMX6SX_CLK_SDMA 195
|
||||||
|
#define IMX6SX_CLK_SPBA 196
|
||||||
|
#define IMX6SX_CLK_SPDIF 197
|
||||||
|
#define IMX6SX_CLK_SSI1_IPG 198
|
||||||
|
#define IMX6SX_CLK_SSI2_IPG 199
|
||||||
|
#define IMX6SX_CLK_SSI3_IPG 200
|
||||||
|
#define IMX6SX_CLK_SSI1 201
|
||||||
|
#define IMX6SX_CLK_SSI2 202
|
||||||
|
#define IMX6SX_CLK_SSI3 203
|
||||||
|
#define IMX6SX_CLK_UART_IPG 204
|
||||||
|
#define IMX6SX_CLK_UART_SERIAL 205
|
||||||
|
#define IMX6SX_CLK_SAI1 206
|
||||||
|
#define IMX6SX_CLK_SAI2 207
|
||||||
|
#define IMX6SX_CLK_USBOH3 208
|
||||||
|
#define IMX6SX_CLK_USDHC1 209
|
||||||
|
#define IMX6SX_CLK_USDHC2 210
|
||||||
|
#define IMX6SX_CLK_USDHC3 211
|
||||||
|
#define IMX6SX_CLK_USDHC4 212
|
||||||
|
#define IMX6SX_CLK_EIM_SLOW 213
|
||||||
|
#define IMX6SX_CLK_PWM8 214
|
||||||
|
#define IMX6SX_CLK_VADC 215
|
||||||
|
#define IMX6SX_CLK_GIS 216
|
||||||
|
#define IMX6SX_CLK_I2C4 217
|
||||||
|
#define IMX6SX_CLK_PWM5 218
|
||||||
|
#define IMX6SX_CLK_PWM6 219
|
||||||
|
#define IMX6SX_CLK_PWM7 220
|
||||||
|
#define IMX6SX_CLK_CKO1 221
|
||||||
|
#define IMX6SX_CLK_CKO2 222
|
||||||
|
#define IMX6SX_CLK_IPP_DI0 223
|
||||||
|
#define IMX6SX_CLK_IPP_DI1 224
|
||||||
|
#define IMX6SX_CLK_ENET_AHB 225
|
||||||
|
#define IMX6SX_CLK_OCRAM_PODF 226
|
||||||
|
#define IMX6SX_CLK_GPT_3M 227
|
||||||
|
#define IMX6SX_CLK_ENET_PTP 228
|
||||||
|
#define IMX6SX_CLK_ENET_PTP_REF 229
|
||||||
|
#define IMX6SX_CLK_ENET2_REF 230
|
||||||
|
#define IMX6SX_CLK_ENET2_REF_125M 231
|
||||||
|
#define IMX6SX_CLK_AUDIO 232
|
||||||
|
#define IMX6SX_CLK_LVDS1_SEL 233
|
||||||
|
#define IMX6SX_CLK_LVDS1_OUT 234
|
||||||
|
#define IMX6SX_CLK_ASRC_IPG 235
|
||||||
|
#define IMX6SX_CLK_ASRC_MEM 236
|
||||||
|
#define IMX6SX_CLK_SAI1_IPG 237
|
||||||
|
#define IMX6SX_CLK_SAI2_IPG 238
|
||||||
|
#define IMX6SX_CLK_ESAI_IPG 239
|
||||||
|
#define IMX6SX_CLK_ESAI_MEM 240
|
||||||
|
#define IMX6SX_CLK_LVDS1_IN 241
|
||||||
|
#define IMX6SX_CLK_ANACLK1 242
|
||||||
|
#define IMX6SX_PLL1_BYPASS_SRC 243
|
||||||
|
#define IMX6SX_PLL2_BYPASS_SRC 244
|
||||||
|
#define IMX6SX_PLL3_BYPASS_SRC 245
|
||||||
|
#define IMX6SX_PLL4_BYPASS_SRC 246
|
||||||
|
#define IMX6SX_PLL5_BYPASS_SRC 247
|
||||||
|
#define IMX6SX_PLL6_BYPASS_SRC 248
|
||||||
|
#define IMX6SX_PLL7_BYPASS_SRC 249
|
||||||
|
#define IMX6SX_CLK_PLL1 250
|
||||||
|
#define IMX6SX_CLK_PLL2 251
|
||||||
|
#define IMX6SX_CLK_PLL3 252
|
||||||
|
#define IMX6SX_CLK_PLL4 253
|
||||||
|
#define IMX6SX_CLK_PLL5 254
|
||||||
|
#define IMX6SX_CLK_PLL6 255
|
||||||
|
#define IMX6SX_CLK_PLL7 256
|
||||||
|
#define IMX6SX_PLL1_BYPASS 257
|
||||||
|
#define IMX6SX_PLL2_BYPASS 258
|
||||||
|
#define IMX6SX_PLL3_BYPASS 259
|
||||||
|
#define IMX6SX_PLL4_BYPASS 260
|
||||||
|
#define IMX6SX_PLL5_BYPASS 261
|
||||||
|
#define IMX6SX_PLL6_BYPASS 262
|
||||||
|
#define IMX6SX_PLL7_BYPASS 263
|
||||||
|
#define IMX6SX_CLK_SPDIF_GCLK 264
|
||||||
|
#define IMX6SX_CLK_CLK_END 265
|
||||||
|
|
||||||
|
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
|
||||||
@ -300,8 +300,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
|
|||||||
/* Set magic number */
|
/* Set magic number */
|
||||||
fhdr_v1->app_code_barker = APP_CODE_BARKER;
|
fhdr_v1->app_code_barker = APP_CODE_BARKER;
|
||||||
|
|
||||||
/* TODO: check i.MX image V1 handling, for now use 'old' style */
|
hdr_base = entry_point - imximage_init_loadsize + flash_offset;
|
||||||
hdr_base = entry_point - 4096;
|
|
||||||
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
|
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
|
||||||
fhdr_v1->app_code_jump_vector = entry_point;
|
fhdr_v1->app_code_jump_vector = entry_point;
|
||||||
|
|
||||||
@ -833,18 +832,19 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
|
|||||||
/* Parse dcd configuration file */
|
/* Parse dcd configuration file */
|
||||||
dcd_len = parse_cfg_file(imxhdr, params->imagename);
|
dcd_len = parse_cfg_file(imxhdr, params->imagename);
|
||||||
|
|
||||||
if (imximage_version == IMXIMAGE_V2) {
|
if (imximage_version == IMXIMAGE_V1)
|
||||||
|
header_size = sizeof(flash_header_v1_t);
|
||||||
|
else {
|
||||||
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
|
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
|
||||||
if (!plugin_image)
|
if (!plugin_image)
|
||||||
header_size += sizeof(dcd_v2_t);
|
header_size += sizeof(dcd_v2_t);
|
||||||
else
|
else
|
||||||
header_size += MAX_PLUGIN_CODE_SIZE;
|
header_size += MAX_PLUGIN_CODE_SIZE;
|
||||||
|
|
||||||
if (imximage_init_loadsize < imximage_ivt_offset + header_size)
|
|
||||||
imximage_init_loadsize = imximage_ivt_offset +
|
|
||||||
header_size;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (imximage_init_loadsize < imximage_ivt_offset + header_size)
|
||||||
|
imximage_init_loadsize = imximage_ivt_offset + header_size;
|
||||||
|
|
||||||
/* Set the imx header */
|
/* Set the imx header */
|
||||||
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
|
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
|
||||||
|
|
||||||
@ -913,23 +913,21 @@ static int imximage_generate(struct image_tool_params *params,
|
|||||||
/* Parse dcd configuration file */
|
/* Parse dcd configuration file */
|
||||||
parse_cfg_file(&imximage_header, params->imagename);
|
parse_cfg_file(&imximage_header, params->imagename);
|
||||||
|
|
||||||
/* TODO: check i.MX image V1 handling, for now use 'old' style */
|
if (imximage_version == IMXIMAGE_V1)
|
||||||
if (imximage_version == IMXIMAGE_V1) {
|
header_size = sizeof(imx_header_v1_t);
|
||||||
alloc_len = 4096;
|
else {
|
||||||
header_size = 4096;
|
|
||||||
} else {
|
|
||||||
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
|
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
|
||||||
if (!plugin_image)
|
if (!plugin_image)
|
||||||
header_size += sizeof(dcd_v2_t);
|
header_size += sizeof(dcd_v2_t);
|
||||||
else
|
else
|
||||||
header_size += MAX_PLUGIN_CODE_SIZE;
|
header_size += MAX_PLUGIN_CODE_SIZE;
|
||||||
|
|
||||||
if (imximage_init_loadsize < imximage_ivt_offset + header_size)
|
|
||||||
imximage_init_loadsize = imximage_ivt_offset +
|
|
||||||
header_size;
|
|
||||||
alloc_len = imximage_init_loadsize - imximage_ivt_offset;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (imximage_init_loadsize < imximage_ivt_offset + header_size)
|
||||||
|
imximage_init_loadsize = imximage_ivt_offset + header_size;
|
||||||
|
|
||||||
|
alloc_len = imximage_init_loadsize - imximage_ivt_offset;
|
||||||
|
|
||||||
if (alloc_len < header_size) {
|
if (alloc_len < header_size) {
|
||||||
fprintf(stderr, "%s: header error\n",
|
fprintf(stderr, "%s: header error\n",
|
||||||
params->cmdname);
|
params->cmdname);
|
||||||
@ -959,11 +957,7 @@ static int imximage_generate(struct image_tool_params *params,
|
|||||||
|
|
||||||
pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
|
pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
|
||||||
|
|
||||||
/* TODO: check i.MX image V1 handling, for now use 'old' style */
|
return pad_len;
|
||||||
if (imximage_version == IMXIMAGE_V1)
|
|
||||||
return 0;
|
|
||||||
else
|
|
||||||
return pad_len;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user