net: sh-eth: Add support Gigabit of SH7734
SH7734 support GMII. This add register infomation and the function which enable GMII. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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@ -348,7 +348,7 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
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phydev = phy_connect(
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miiphy_get_dev_by_name(dev->name),
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port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
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port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
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port_info->phydev = phydev;
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phy_config(phydev);
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@ -405,6 +405,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(TPAUSER_UNLIMITED, TPAUSER(port));
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#endif
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#if defined(CONFIG_CPU_SH7734)
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outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
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#endif
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/* Configure phy */
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ret = sh_eth_phy_config(eth);
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if (ret) {
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@ -434,6 +437,12 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(0, RTRATE(port));
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#endif
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}
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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else if (phy->speed == 1000) {
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printf(SHETHER_NAME ": 1000Base/");
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outl(GECMR_1000B, GECMR(port));
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}
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#endif
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/* Check if full duplex mode is supported by the phy */
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if (phy->duplex) {
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@ -225,6 +225,7 @@ struct sh_eth_dev {
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#define GECMR(port) (BASE_IO_ADDR + 0x05b0)
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#define MAHR(port) (BASE_IO_ADDR + 0x05C0)
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#define MALR(port) (BASE_IO_ADDR + 0x05C8)
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#define RMII_MII(port) (BASE_IO_ADDR + 0x0790)
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#endif
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