mpc83xx: Get rid of CONFIG_SYS_LBC_*
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value
of either 0x00040000 or 0x00000000.
CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.
CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.
CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).
To simplify the configuration files, hardcode the setting of these
values for mpc83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six
@@ -121,11 +121,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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/*
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* FLASH on the Local Bus
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*/
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@@ -186,16 +186,6 @@
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
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| (0xFF << LBCR_BMT_SHIFT) \
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| 0xF) /* 0x0004ff0f */
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
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/* drivers/mtd/nand/raw/nand.c */
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#if defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_NAND_BASE 0xFFF00000
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@@ -159,16 +159,6 @@
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
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| (0xFF << LBCR_BMT_SHIFT) \
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| 0xF) /* 0x0004ff0f */
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
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/* drivers/mtd/nand/nand.c */
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#define CONFIG_SYS_NAND_BASE 0xE2800000
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@@ -116,11 +116,7 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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#define CONFIG_FSL_ELBC 1
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#define CONFIG_FSL_ELBC
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/*
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* FLASH on the Local Bus
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@@ -113,11 +113,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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@@ -113,11 +113,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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@@ -153,14 +153,6 @@
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* Serial Port
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*/
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@@ -150,14 +150,6 @@
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
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*/
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@@ -250,19 +250,6 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32*/
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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/*
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* Serial Port
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*/
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@@ -134,10 +134,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_FSL_ELBC 1
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/*
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@@ -158,10 +158,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_FSL_ELBC 1
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/*
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@@ -96,14 +96,6 @@
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: no DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
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/*
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@@ -110,11 +110,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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/*
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* FLASH on the Local Bus
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*/
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@@ -36,15 +36,6 @@
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- CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
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(0xFF << LBCR_BMT_SHIFT) |\
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0xF)
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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/*
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* Internal Definitions
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*/
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@@ -289,11 +289,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
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@@ -289,11 +289,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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@@ -341,11 +341,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/* must be after the include because KMBEC_FPGA is otherwise undefined */
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
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@@ -289,11 +289,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
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@@ -333,11 +333,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000
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@@ -125,11 +125,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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/*
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* FLASH on the Local Bus
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*/
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@@ -123,14 +123,6 @@
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
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/*
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@@ -110,11 +110,6 @@
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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/*
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* FLASH on the Local Bus
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*/
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@@ -286,11 +286,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000
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@@ -289,11 +289,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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@@ -289,11 +289,6 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
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@@ -128,13 +128,6 @@
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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/*
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* NAND settings
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*/
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@@ -96,14 +96,6 @@
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: no DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
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/*
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Reference in New Issue
Block a user