From 42653b826adb319a1df06e24ef26096b2a5d9d2a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Oct 2008 21:58:49 -0500 Subject: [PATCH] Revert "85xx: Using proper I2C source clock divider for MPC8544" This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. The fix introduced by this patch is not correct. The problem is that the documentation is not correct for the MPC8544 with regards to which bit in PORDEVSR2 is for the SEC_CFG. Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 70dfad0321..485ba20fd7 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 2; - else gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2;