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reset: Convert ipq4019 driver to a generic Qcom driver

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Since the base functionality remains the same for a reset driver on Qcom
SoCs, so leverage that to convert ipq4019 specific reset driver to a
generic Qcom reset driver. With that one just need to provide SoC specific
reset table.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg 2022-08-04 19:57:11 +05:30 committed by Tom Rini
parent 0b746d287c
commit 42588276b3
3 changed files with 30 additions and 27 deletions
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9
drivers/reset/Kconfig
View File

@ -156,13 +156,12 @@ config RESET_IMX7
help help
Support for reset controller on i.MX7/8 SoCs. Support for reset controller on i.MX7/8 SoCs.
config RESET_IPQ419 config RESET_QCOM
bool "Reset driver for Qualcomm IPQ40xx SoCs" bool "Reset driver for Qualcomm SoCs"
depends on DM_RESET && ARCH_IPQ40XX depends on DM_RESET && (ARCH_SNAPDRAGON || ARCH_IPQ40XX)
default y default y
help help
Support for reset controller on Qualcomm Support for reset controller on Qualcomm SoCs.
IPQ40xx SoCs.
config RESET_SIFIVE config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's" bool "Reset Driver for SiFive SoC's"

2
drivers/reset/Makefile
View File

@ -24,7 +24,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o obj-$(CONFIG_RESET_QCOM) += reset-qcom.o
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o

46
drivers/reset/reset-ipq4019.c → drivers/reset/reset-qcom.c
View File

@ -1,8 +1,10 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Copyright (c) 2020 Sartura Ltd. * Copyright (c) 2020 Sartura Ltd.
* Copyright (c) 2022 Linaro Ltd.
* *
* Author: Robert Marko <robert.marko@sartura.hr> * Author: Robert Marko <robert.marko@sartura.hr>
* Sumit Garg <sumit.garg@linaro.org>
* *
* Based on Linux driver * Based on Linux driver
*/ */
@ -10,12 +12,11 @@
#include <asm/io.h> #include <asm/io.h>
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>
#include <dt-bindings/reset/qcom,ipq4019-reset.h>
#include <reset-uclass.h> #include <reset-uclass.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <malloc.h> #include <malloc.h>
struct ipq4019_reset_priv { struct qcom_reset_priv {
phys_addr_t base; phys_addr_t base;
}; };
@ -24,7 +25,9 @@ struct qcom_reset_map {
u8 bit; u8 bit;
}; };
static const struct qcom_reset_map gcc_ipq4019_resets[] = { #ifdef CONFIG_ARCH_IPQ40XX
#include <dt-bindings/reset/qcom,ipq4019-reset.h>
static const struct qcom_reset_map gcc_qcom_resets[] = {
[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
@ -97,11 +100,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[GCC_MPM_BCR] = {0x24000, 0}, [GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0}, [GCC_SPDM_BCR] = {0x25000, 0},
}; };
#endif
static int ipq4019_reset_assert(struct reset_ctl *rst) static int qcom_reset_assert(struct reset_ctl *rst)
{ {
struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev); struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
const struct qcom_reset_map *reset_map = gcc_ipq4019_resets; const struct qcom_reset_map *reset_map = gcc_qcom_resets;
const struct qcom_reset_map *map; const struct qcom_reset_map *map;
u32 value; u32 value;
@ -114,10 +118,10 @@ static int ipq4019_reset_assert(struct reset_ctl *rst)
return 0; return 0;
} }
static int ipq4019_reset_deassert(struct reset_ctl *rst) static int qcom_reset_deassert(struct reset_ctl *rst)
{ {
struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev); struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
const struct qcom_reset_map *reset_map = gcc_ipq4019_resets; const struct qcom_reset_map *reset_map = gcc_qcom_resets;
const struct qcom_reset_map *map; const struct qcom_reset_map *map;
u32 value; u32 value;
@ -130,19 +134,19 @@ static int ipq4019_reset_deassert(struct reset_ctl *rst)
return 0; return 0;
} }
static const struct reset_ops ipq4019_reset_ops = { static const struct reset_ops qcom_reset_ops = {
.rst_assert = ipq4019_reset_assert, .rst_assert = qcom_reset_assert,
.rst_deassert = ipq4019_reset_deassert, .rst_deassert = qcom_reset_deassert,
}; };
static const struct udevice_id ipq4019_reset_ids[] = { static const struct udevice_id qcom_reset_ids[] = {
{ .compatible = "qcom,gcc-reset-ipq4019" }, { .compatible = "qcom,gcc-reset-ipq4019" },
{ } { }
}; };
static int ipq4019_reset_probe(struct udevice *dev) static int qcom_reset_probe(struct udevice *dev)
{ {
struct ipq4019_reset_priv *priv = dev_get_priv(dev); struct qcom_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev); priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE) if (priv->base == FDT_ADDR_T_NONE)
@ -151,11 +155,11 @@ static int ipq4019_reset_probe(struct udevice *dev)
return 0; return 0;
} }
U_BOOT_DRIVER(ipq4019_reset) = { U_BOOT_DRIVER(qcom_reset) = {
.name = "ipq4019_reset", .name = "qcom_reset",
.id = UCLASS_RESET, .id = UCLASS_RESET,
.of_match = ipq4019_reset_ids, .of_match = qcom_reset_ids,
.ops = &ipq4019_reset_ops, .ops = &qcom_reset_ops,
.probe = ipq4019_reset_probe, .probe = qcom_reset_probe,
.priv_auto = sizeof(struct ipq4019_reset_priv), .priv_auto = sizeof(struct qcom_reset_priv),
}; };