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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

Browse Source 
* 'master' of git://git.denx.de/u-boot-ppc4xx:
  powerpc/ppc4xx: Remove typedefs for gdsys FPGA
  powerpc/ppc4xx: Fix typo in gdsys_fpga.h
  powerpc/ppc4xx: Update gdsys board configurations
  powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
  powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
  powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
  powerpc/ppc4xx: Adjust environment size on neo
This commit is contained in:
Wolfgang Denk 2012-04-30 16:55:25 +02:00
commit 4212657c53
21 changed files with 507 additions and 301 deletions
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45
board/gdsys/405ep/405ep.c
View File

@ -28,12 +28,9 @@
#include <asm/ppc4xx-gpio.h>
#include <asm/global_data.h>
#include "405ep.h"
#include <gdsys_fpga.h>
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev)
int board_early_init_f(void)
{
unsigned k;
unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] = 0;
@ -73,26 +69,29 @@ int board_early_init_f(void)
* -> ca. 15 us
*/
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
int board_early_init_r(void)
{
unsigned k;
unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] = 0;
/*
* setup io-latches for reset
* reset FPGA
*/
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
gd405ep_init();
/*
* set "startup-finished"-gpios
*/
gpio_write_bit(21, 0);
gpio_write_bit(22, 1);
gd405ep_set_fpga_reset(1);
gd405ep_setup_hw();
/*
* wait for fpga-done
*/
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ctr = 0;
while (!(in_le16((void *)LATCH2_BASE)
& CONFIG_SYS_FPGA_DONE(k))) {
while (!gd405ep_get_fpga_done(k)) {
udelay(100000);
if (ctr++ > 5) {
gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
@ -101,15 +100,13 @@ int board_early_init_f(void)
}
}
/*
* setup io-latches for boot (stop reset)
*/
udelay(10);
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
gd405ep_set_fpga_reset(0);
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
struct ihs_fpga *fpga =
(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
u16 *reflection_target = &fpga->reflection_low;
#else

10
board/gdsys/405ep/405ep.h Normal file
View File

@ -0,0 +1,10 @@
#ifndef __405EP_H_
#define __405EP_H_
/* functions to be provided by board implementation */
void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);
#endif /* __405EP_H_ */

1
board/gdsys/405ep/Makefile
View File

@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-$(CONFIG_NEO) += neo.o
COBJS-$(CONFIG_IO) += io.o
COBJS-$(CONFIG_IOCON) += iocon.o
COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o

80
board/gdsys/405ep/dlvision-10g.c
View File

@ -26,16 +26,20 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <dtt.h>
#include "405ep.h"
#include <gdsys_fpga.h>
#include "../common/osd.h"
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
#define LATCH2_MC2_PRESENT_N 0x0080
#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
#define LATCH2_MC2_PRESENT_N 0x0080
enum {
UNITTYPE_VIDEO_USER = 0,
UNITTYPE_MAIN_USER = 1,
@ -46,6 +50,8 @@ enum {
enum {
HWVER_101 = 0,
HWVER_110 = 1,
HWVER_120 = 2,
HWVER_130 = 3,
};
enum {
@ -65,6 +71,14 @@ enum {
RAM_DDR2_64 = 2,
};
int misc_init_r(void)
{
/* startup fans */
dtt_init();
return 0;
}
static unsigned int get_hwver(void)
{
u16 latch3 = in_le16((void *)LATCH3_BASE);
@ -81,7 +95,7 @@ static unsigned int get_mc2_present(void)
static void print_fpga_info(unsigned dev)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
@ -146,7 +160,15 @@ static void print_fpga_info(unsigned dev)
break;
case HWVER_110:
printf(" HW-Ver 1.10\n");
printf(" HW-Ver 1.10-1.12\n");
break;
case HWVER_120:
printf(" HW-Ver 1.20\n");
break;
case HWVER_130:
printf(" HW-Ver 1.30\n");
break;
default:
@ -223,32 +245,31 @@ static void print_fpga_info(unsigned dev)
*/
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
char *s = getenv("serial#");
printf("Board: ");
puts("Board: ");
printf("DLVision 10G");
puts("DLVision 10G");
if (i > 0) {
if (s != NULL) {
puts(", serial# ");
puts(buf);
puts(s);
}
puts("\n");
print_fpga_info(0);
if (get_mc2_present())
print_fpga_info(1);
return 0;
}
int last_stage_init(void)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
print_fpga_info(0);
if (get_mc2_present())
print_fpga_info(1);
if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
return 0;
@ -261,3 +282,32 @@ int last_stage_init(void)
return 0;
}
void gd405ep_init(void)
{
}
void gd405ep_set_fpga_reset(unsigned state)
{
if (state) {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
} else {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
}
}
void gd405ep_setup_hw(void)
{
/*
* set "startup-finished"-gpios
*/
gpio_write_bit(21, 0);
gpio_write_bit(22, 1);
}
int gd405ep_get_fpga_done(unsigned fpga)
{
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
}

79
board/gdsys/405ep/io.c
View File

@ -27,10 +27,16 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <dtt.h>
#include <miiphy.h>
#include "405ep.h"
#include <gdsys_fpga.h>
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
#define PHYREG_CONTROL 0
#define PHYREG_PAGE_ADDRESS 22
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
@ -47,6 +53,14 @@ enum {
HWVER_122 = 3,
};
int misc_init_r(void)
{
/* startup fans */
dtt_init();
return 0;
}
int configure_gbit_phy(unsigned char addr)
{
unsigned short value;
@ -87,9 +101,23 @@ err_out:
*/
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
puts("Board: CATCenter Io");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
puts("\n");
return 0;
}
static void print_fpga_info(void)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
@ -103,15 +131,7 @@ int checkboard(void)
feature_channels = fpga_features & 0x007f;
feature_expansion = fpga_features & (1<<15);
printf("Board: ");
printf("CATCenter Io");
if (i > 0) {
puts(", serial# ");
puts(buf);
}
puts("\n ");
puts("FPGA: ");
switch (unit_type) {
case UNITTYPE_CCD_SWITCH:
@ -152,8 +172,6 @@ int checkboard(void)
printf(" %d channel(s)", feature_channels);
printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
return 0;
}
/*
@ -161,9 +179,11 @@ int checkboard(void)
*/
int last_stage_init(void)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
print_fpga_info();
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
bb_miiphy_read, bb_miiphy_write);
@ -175,3 +195,32 @@ int last_stage_init(void)
return 0;
}
void gd405ep_init(void)
{
}
void gd405ep_set_fpga_reset(unsigned state)
{
if (state) {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
} else {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
}
}
void gd405ep_setup_hw(void)
{
/*
* set "startup-finished"-gpios
*/
gpio_write_bit(21, 0);
gpio_write_bit(22, 1);
}
int gd405ep_get_fpga_done(unsigned fpga)
{
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
}

70
board/gdsys/405ep/iocon.c
View File

@ -27,10 +27,15 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include "405ep.h"
#include <gdsys_fpga.h>
#include "../common/osd.h"
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
enum {
UNITTYPE_MAIN_SERVER = 0,
UNITTYPE_MAIN_USER = 1,
@ -69,9 +74,25 @@ enum {
*/
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
puts("Board: ");
puts("IoCon");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
puts("\n");
return 0;
}
static void print_fpga_info(void)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
@ -95,16 +116,6 @@ int checkboard(void)
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
printf("Board: ");
printf("IoCon");
if (i > 0) {
puts(", serial# ");
puts(buf);
}
puts("\n ");
switch (unit_type) {
case UNITTYPE_MAIN_USER:
printf("Mainchannel");
@ -205,12 +216,12 @@ int checkboard(void)
printf(", %d carrier(s)", feature_carriers);
printf(", %d video channel(s)\n", feature_video_channels);
return 0;
}
int last_stage_init(void)
{
print_fpga_info();
return osd_probe(0);
}
@ -231,3 +242,32 @@ int fpga_gpio_get(int pin)
{
return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
}
void gd405ep_init(void)
{
}
void gd405ep_set_fpga_reset(unsigned state)
{
if (state) {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
} else {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
}
}
void gd405ep_setup_hw(void)
{
/*
* set "startup-finished"-gpios
*/
gpio_write_bit(21, 0);
gpio_write_bit(22, 1);
}
int gd405ep_get_fpga_done(unsigned fpga)
{
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
}

161
board/gdsys/405ep/neo.c Normal file
View File

@ -0,0 +1,161 @@
/*
* (C) Copyright 2011
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <dtt.h>
#include "405ep.h"
#include <gdsys_fpga.h>
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
enum {
UNITTYPE_CCX16 = 1,
UNITTYPE_CCIP216 = 2,
};
enum {
HWVER_300 = 3,
};
int misc_init_r(void)
{
/* startup fans */
dtt_init();
return 0;
}
int checkboard(void)
{
char *s = getenv("serial#");
puts("Board: CATCenter Neo");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
puts("\n");
return 0;
}
static void print_fpga_info(void)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
int fpga_state = get_fpga_state(0);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_channels;
puts("FPGA: ");
if (fpga_state & FPGA_STATE_DONE_FAILED) {
printf(" done timed out\n");
return;
}
if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
printf(" refelectione test failed\n");
return;
}
unit_type = (versions & 0xf000) >> 12;
hardware_version = versions & 0x000f;
feature_channels = fpga_features & 0x007f;
switch (unit_type) {
case UNITTYPE_CCX16:
printf("CCX-Switch");
break;
default:
printf("UnitType %d(not supported)", unit_type);
break;
}
switch (hardware_version) {
case HWVER_300:
printf(" HW-Ver 3.00-3.12\n");
break;
default:
printf(" HW-Ver %d(not supported)\n",
hardware_version);
break;
}
printf(" FPGA V %d.%02d, features:",
fpga_version / 100, fpga_version % 100);
printf(" %d channel(s)\n", feature_channels);
}
int last_stage_init(void)
{
print_fpga_info();
return 0;
}
void gd405ep_init(void)
{
}
void gd405ep_set_fpga_reset(unsigned state)
{
if (state) {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
} else {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
}
}
void gd405ep_setup_hw(void)
{
/*
* set "startup-finished"-gpios
*/
gpio_write_bit(21, 0);
gpio_write_bit(22, 1);
}
int gd405ep_get_fpga_done(unsigned fpga)
{
/*
* Neo hardware has no FPGA-DONE GPIO
*/
return 1;
}

3
board/gdsys/405ex/405ex.c
View File

@ -219,7 +219,8 @@ int board_early_init_r(void)
gd405ex_set_fpga_reset(0);
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
struct ihs_fpga *fpga =
(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
u16 *reflection_target = &fpga->reflection_low;
#else

6
board/gdsys/405ex/io64.c
View File

@ -100,7 +100,7 @@ int misc_init_r(void)
static void print_fpga_info(unsigned dev)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
@ -242,8 +242,8 @@ int last_stage_init(void)
{
unsigned int k;
unsigned int fpga;
ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
int failed = 0;
char str_phys[] = "Setup PHYs -";
char str_serdes[] = "Start SERDES blocks";

18
board/gdsys/common/osd.c
View File

@ -70,8 +70,8 @@ enum {
#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
ihs_i2c_t *i2c = &fpga->i2c;
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
struct ihs_i2c *i2c = &fpga->i2c;
while (in_le16(&fpga->extended_interrupt) & (1 << 12))
;
@ -81,8 +81,8 @@ static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
ihs_i2c_t *i2c = &fpga->i2c;
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
struct ihs_i2c *i2c = &fpga->i2c;
unsigned int ctr = 0;
while (in_le16(&fpga->extended_interrupt) & (1 << 12))
@ -129,7 +129,7 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
static void mpc92469ac_set(unsigned screen, unsigned int fout)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
unsigned int n;
unsigned int m;
unsigned int bitval = 0;
@ -265,8 +265,8 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
static int osd_write_videomem(unsigned screen, unsigned offset,
u16 *data, size_t charcount)
{
ihs_fpga_t *fpga =
(ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
struct ihs_fpga *fpga =
(struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
unsigned int k;
for (k = 0; k < charcount; ++k) {
@ -318,8 +318,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int osd_probe(unsigned screen)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
ihs_osd_t *osd = &fpga->osd;
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
struct ihs_osd *osd = &fpga->osd;
u16 version = in_le16(&osd->version);
u16 features = in_le16(&osd->features);
unsigned width;

45
board/gdsys/neo/Makefile
View File

@ -1,45 +0,0 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

102
board/gdsys/neo/neo.c
View File

@ -1,102 +0,0 @@
/*
* (C) Copyright 2007-2008
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#define HWTYPE_CCX16 1
#define HWREV_300 3
int board_early_init_f(void)
{
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
u8 unit_type;
u8 hardware_cpu_ports;
u8 hardware_con_ports;
u8 hardware_version;
printf("Board: CATCenter Neo");
if (i > 0) {
puts(", serial# ");
puts(buf);
}
puts("\n ");
unit_type = (val & 0xf000) >> 12;
hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
hardware_version = val & 0x000f;
switch (unit_type) {
case HWTYPE_CCX16:
printf("CCX16-FPGA (80 UARTs)");
break;
default:
printf("UnitType %d, unsupported", unit_type);
break;
}
printf(", %d cpu ports, %d console ports,",
hardware_cpu_ports, hardware_con_ports);
switch (hardware_version) {
case HWREV_300:
printf(" HW-Ver 3.00\n");
break;
default:
printf(" HW-Ver %d, unsupported\n",
hardware_version);
break;
}
return 0;
}

2
boards.cfg
View File

@ -990,7 +990,7 @@ intip powerpc ppc4xx intip gdsys
io powerpc ppc4xx 405ep gdsys
io64 powerpc ppc4xx 405ex gdsys
iocon powerpc ppc4xx 405ep gdsys
neo powerpc ppc4xx - gdsys
neo powerpc ppc4xx 405ep gdsys
icon powerpc ppc4xx - mosaixtech
MIP405 powerpc ppc4xx mip405 mpl
MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T

9
include/configs/dlvision-10g.h
View File

@ -34,10 +34,12 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
#define CONFIG_IDENT_STRING " dlvision-10g 0.03"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@ -80,6 +82,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*
@ -115,7 +118,7 @@
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }

4
include/configs/gdppc440etx.h
View File

@ -50,6 +50,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)

4
include/configs/intip.h
View File

@ -37,10 +37,10 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
#define CONFIG_IDENT_STRING " devconcenter 0.05"
#define CONFIG_IDENT_STRING " devconcenter 0.06"
#else
#define CONFIG_HOSTNAME intip
#define CONFIG_IDENT_STRING " intip 0.05"
#define CONFIG_IDENT_STRING " intip 0.06"
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */

13
include/configs/io.h
View File

@ -34,11 +34,13 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io
#define CONFIG_IDENT_STRING " io 0.04"
#define CONFIG_IDENT_STRING " io 0.05"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@ -48,6 +50,10 @@
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR " "
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
@ -76,6 +82,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*

2
include/configs/io64.h
View File

@ -53,7 +53,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io64
#define CONFIG_IDENT_STRING " io64 0.01"
#define CONFIG_IDENT_STRING " io64 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F

9
include/configs/iocon.h
View File

@ -34,10 +34,11 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
#define CONFIG_IDENT_STRING " iocon 0.03"
#define CONFIG_IDENT_STRING " iocon 0.04"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@ -48,6 +49,10 @@
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR " "
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */

96
include/configs/neo.h
View File

@ -35,9 +35,13 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME neo
#define CONFIG_IDENT_STRING " neo 0.01"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@ -149,53 +153,53 @@
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CONFIG_ENV_ADDR 0xFFF00000
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/*
* PPC405 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
} \
#define CONFIG_SYS_4xx_GPIO_TABLE { \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
} \
}
/*
@ -226,12 +230,22 @@
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_FPGA_BASE 0x7f100000
#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x92015480
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_COUNT 1
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0x92015480
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_LATCH0_RESET 0xffff
#define CONFIG_SYS_LATCH0_BOOT 0xffff
#define CONFIG_SYS_LATCH1_RESET 0xffbf
#define CONFIG_SYS_LATCH1_BOOT 0xffff
#endif /* __CONFIG_H */

49
include/gdsys_fpga.h
View File

@ -35,20 +35,20 @@ enum {
int get_fpga_state(unsigned dev);
void print_fpga_state(unsigned dev);
typedef struct ihs_gpio {
struct ihs_gpio {
u16 read;
u16 clear;
u16 set;
} ihs_gpio_t;
};
typedef struct ihs_i2c {
struct ihs_i2c {
u16 write_mailbox;
u16 write_mailbox_ext;
u16 read_mailbox;
u16 read_mailbox_ext;
} ihs_i2c_t;
};
typedef struct ihs_osd {
struct ihs_osd {
u16 version;
u16 features;
u16 control;
@ -56,10 +56,21 @@ typedef struct ihs_osd {
u16 xy_scale;
u16 x_pos;
u16 y_pos;
} ihs_osd_t;
};
#ifdef CONFIG_NEO
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_features; /* 0x0004 */
u16 fpga_version; /* 0x0006 */
u16 reserved_0[8187]; /* 0x0008 */
u16 reflection_high; /* 0x3ffe */
};
#endif
#ifdef CONFIG_IO
typedef struct ihs_fpga {
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_features; /* 0x0004 */
@ -68,11 +79,11 @@ typedef struct ihs_fpga {
u16 quad_serdes_reset; /* 0x0012 */
u16 reserved_1[8181]; /* 0x0014 */
u16 reflection_high; /* 0x3ffe */
} ihs_fpga_t;
};
#endif
#ifdef CONFIG_IO64
typedef struct ihs_fpga {
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_features; /* 0x0004 */
@ -87,30 +98,30 @@ typedef struct ihs_fpga {
u16 ch0_hicb_config_int;/* 0x0502 */
u16 reserved_3[7549]; /* 0x0504 */
u16 reflection_high; /* 0x3ffe */
} ihs_fpga_t;
};
#endif
#ifdef CONFIG_IOCON
typedef struct ihs_fpga {
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[6]; /* 0x0008 */
ihs_gpio_t gpio; /* 0x0014 */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
u16 reserved_1[19]; /* 0x001c */
u16 videocontrol; /* 0x0042 */
u16 reserved_2[93]; /* 0x0044 */
u16 reflection_high; /* 0x00fe */
ihs_osd_t osd; /* 0x0100 */
u16 reserved_3[88]; /* 0x010e */
struct ihs_osd osd; /* 0x0100 */
u16 reserved_3[889]; /* 0x010e */
u16 videomem; /* 0x0800 */
} ihs_fpga_t;
};
#endif
#ifdef CONFIG_DLVISION_10G
typedef struct ihs_fpga {
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
@ -118,16 +129,16 @@ typedef struct ihs_fpga {
u16 reserved_0[10]; /* 0x0008 */
u16 extended_interrupt; /* 0x001c */
u16 reserved_1[9]; /* 0x001e */
ihs_i2c_t i2c; /* 0x0030 */
struct ihs_i2c i2c; /* 0x0030 */
u16 reserved_2[16]; /* 0x0038 */
u16 mpc3w_control; /* 0x0058 */
u16 reserved_3[34]; /* 0x005a */
u16 videocontrol; /* 0x009e */
u16 reserved_4[176]; /* 0x00a0 */
ihs_osd_t osd; /* 0x0200 */
struct ihs_osd osd; /* 0x0200 */
u16 reserved_5[761]; /* 0x020e */
u16 videomem; /* 0x0800 */
} ihs_fpga_t;
};
#endif
#endif