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ARM: atmel: at91sam9m10g45ek: enable spl support

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Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.

As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
This commit is contained in:
Bo Shen
2015-03-27 14:23:34 +08:00
committed by Andreas Bießmann
parent 72cb3b6b54
commit 41d41a93fb
7 changed files with 194 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

80
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
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@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
@@ -15,6 +16,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <linux/mtd/nand.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void)
}
#endif
#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>
void at91_spl_board_init(void)
{
/*
* On the at91sam9m10g45ek board, the chip wm9711 stays in the
* test mode, so it needs do some action to exit test mode.
*/
at91_periph_clk_enable(ATMEL_ID_PIODE);
at91_set_gpio_output(AT91_PIN_PD7, 0);
at91_set_gpio_output(AT91_PIN_PD8, 0);
at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
#ifdef CONFIG_SYS_USE_MMC
at91_mci_hw_init();
#elif CONFIG_SYS_USE_NANDFLASH
at91sam9m10g45ek_nand_hw_init();
#endif
}
#include <asm/arch/atmel_mpddrc.h>
static void ddr2_conf(struct atmel_mpddr *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
ATMEL_MPDDRC_CR_NR_ROW_14 |
ATMEL_MPDDRC_CR_DQMS_SHARED |
ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
ddr2->rtr = 0x24b;
ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
struct atmel_mpddr ddr2;
unsigned long csa;
ddr2_conf(&ddr2);
/* enable DDR2 clock */
writel(0x4, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&mat->ebicsa);
csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
writel(csa, &mat->ebicsa);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_CS6, &ddr2);
}
#endif
#ifdef CONFIG_CMD_USB
static void at91sam9m10g45ek_usb_hw_init(void)
{